Patents by Inventor Takeshi Sugahara
Takeshi Sugahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240140760Abstract: To provide a drive device for a self-propelled elevator which is capable of moving a car in a vertical direction and a horizontal direction with a simple configuration. The drive device for a self-propelled elevator includes: a rotating body which is rotatably coupled to a back face of a cab; and wheels which are provided on the rotating body so as to sandwich guide surfaces of a rail on a back face side of the cab, which generate, by friction between the wheels and the rail, a force that moves the cab in a vertical direction when a longitudinal direction of the rail is the vertical direction, and which generate, by a friction force between the wheels and the rail, a force that moves the cab in a horizontal direction when the longitudinal direction of the rail is the horizontal direction.Type: ApplicationFiled: March 8, 2021Publication date: May 2, 2024Applicants: Mitsubishi Electric Corporation, Tokyo Institute of TechnologyInventors: Yusuke SUGAHARA, Yukio TAKEDA, Takahiro ISHII, Takeshi MATSUMOTO, Masayuki KAKIO
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Patent number: 11958939Abstract: A polyimide precursor solution contains: an aqueous solvent containing water; particles; and a polyimide precursor, wherein the polyimide precursor has a high molecular weight region A containing a high molecular weight side maximum value and a low molecular weight region B containing a low molecular weight side maximum value in an elution curve obtained by gel permeation chromatography, a weight average molecular weight in the high molecular weight region A is 50,000 or more, a weight average molecular weight in the low molecular weight region B is 10,000 or more and 30,000 or less, and a value of a/(a+b) is 0.60 or more and 0.98 or less in which a represents an area of the high molecular weight region A and b represents an area of the low molecular weight region B.Type: GrantFiled: August 16, 2021Date of Patent: April 16, 2024Assignee: FUJIFILM Business Innovation Corp.Inventors: Kosuke Nakada, Shigeru Seitoku, Takeshi Iwanaga, Tomoyo Okubo, Hajime Sugahara, Hidekazu Hirose
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Publication number: 20140207645Abstract: In one embodiment the present invention relates to a method for structuring a transaction involving a first party having a long position in a security and a second party desiring to acquire short exposure to the security. In one example an agent or intermediary acts between the first party and the second party. In another example the first party and the second party deal directly with one another.Type: ApplicationFiled: November 25, 2013Publication date: July 24, 2014Applicant: Goldman, Sachs & Co.Inventor: James Takeshi Sugahara
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Patent number: 8600853Abstract: In one embodiment the present invention relates to a method for structuring a transaction involving a first party having a long position in a security and a second party desiring to acquire short exposure to the security. In one example an agent or intermediary acts between the first party and the second party. In another example the first party and the second party deal directly with one another.Type: GrantFiled: December 17, 2007Date of Patent: December 3, 2013Assignee: Goldman, Sachs & Co.Inventor: James Takeshi Sugahara
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Patent number: 7933107Abstract: An electrostatic discharge protection circuit device includes a discharge circuit, a trigger circuit and a trigger control circuit. The discharge circuit is connected to a predetermined circuit node of a semiconductor device, and makes discharge when surge voltage is applied to the circuit node. The trigger circuit triggers the discharge circuit to start a discharge operation by the discharge circuit. The trigger control circuit controls a trigger voltage at which the trigger circuit starts a discharge operation by the discharge circuit.Type: GrantFiled: November 21, 2007Date of Patent: April 26, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Takeshi Sugahara
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Patent number: 7882476Abstract: Standard cells without a well potential fixing active region (4T-11 to 4T-14, 4T-21 to 4T-24, 4T-31 to 4T-34, 4T-41 to 4T-44) are read from a library and a circuit is temporarily designed by automatic layout wiring. Then, a change in the substrate potential is estimated from at least one of the number of transistors to be switched at the same timing in the temporarily designed circuit, the sizes of transistors, the transition probability, and the appearance probability. It is determined whether the estimated change in the substrate potential is within a reference value. If the estimated change in the substrate potential has exceeded the reference value, standard cells with a well potential fixing active region (2T-11, 2T-21, 2T-31 and 2T-41) are read from the library and placed in a region where the estimated change in the substrate potential exceeds the reference value. Thereafter, automatic layout wiring is done again, thereby forming a circuit.Type: GrantFiled: September 15, 2005Date of Patent: February 1, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhito Itaka, Koichi Kinoshita, Takeshi Sugahara
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Patent number: 7514728Abstract: In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the second conductivity type are formed. The second well regions are formed in the semiconductor substrate excluding the region where the first well region has been formed. The third well region is formed under the first and second well regions in the semiconductor substrate in such a manner that a part of the third well region under the first well region is removed, thereby connecting the second well regions to one another electrically.Type: GrantFiled: November 30, 2007Date of Patent: April 7, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Sugahara, Yasuhito Itaka
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Publication number: 20090083686Abstract: Standard cells without a well potential fixing active region (4T-11 to 4T-14, 4T-21 to 4T-24, 4T-31 to 4T-34, 4T-41 to 4T-44) are read from a library and a circuit is temporarily designed by automatic layout wiring. Then, a change in the substrate potential is estimated from at least one of the number of transistors to be switched at the same timing in the temporarily designed circuit, the sizes of transistors, the transition probability, and the appearance probability. It is determined whether the estimated change in the substrate potential is within a reference value. If the estimated change in the substrate potential has exceeded the reference value, standard cells with a well potential fixing active region (2T-11, 2T-21, 2T-31 and 2T-41) are read from the library and placed in a region where the estimated change in the substrate potential exceeds the reference value. Thereafter, automatic layout wiring is done again, thereby forming a circuit.Type: ApplicationFiled: September 15, 2005Publication date: March 26, 2009Inventors: Yasuhito Itaka, Koichi Kinoshita, Takeshi Sugahara
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Publication number: 20080180869Abstract: An electrostatic discharge protection circuit device includes a discharge circuit, a trigger circuit and a trigger control circuit. The discharge circuit is connected to a predetermined circuit node of a semiconductor device, and makes discharge when surge voltage is applied to the circuit node. The trigger circuit triggers the discharge circuit to start a discharge operation by the discharge circuit. The trigger control circuit controls a trigger voltage at which the trigger circuit starts a discharge operation by the discharge circuit.Type: ApplicationFiled: November 21, 2007Publication date: July 31, 2008Inventor: Takeshi Sugahara
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Publication number: 20080126268Abstract: In one embodiment the present invention relates to a method for structuring a transaction involving a first party having a long position in a security and a second party desiring to acquire short exposure to the security. In one example an agent or intermediary acts between the first party and the second party. In another example the first party and the second party deal directly with one another.Type: ApplicationFiled: December 17, 2007Publication date: May 29, 2008Inventor: James Takeshi Sugahara
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Patent number: 7368767Abstract: A standard cell is read from a library and automatic layout wiring is performed, thereby configuring a circuit. Next, each cell column in the configured circuit is searched for an empty region. In the empty region in the cell column searched for, a spacer cell or a filler cell is placed. At this time, using the spacer cell or filler cell, the well potential of the standard cells in the cell column is fixed.Type: GrantFiled: March 24, 2005Date of Patent: May 6, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Kinoshita, Yasuhito Itaka, Takeshi Sugahara
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Patent number: 7365377Abstract: In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the second conductivity type are formed. The second well regions are formed in the semiconductor substrate excluding the region where the first well region has been formed. The third well region is formed under the first and second well regions in the semiconductor substrate in such a manner that a part of the third well region under the first well region is removed, thereby connecting the second well regions to one another electrically.Type: GrantFiled: June 27, 2005Date of Patent: April 29, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Sugahara, Yasuhito Itaka
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Publication number: 20080073729Abstract: In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the second conductivity type are formed. The second well regions are formed in the semiconductor substrate excluding the region where the first well region has been formed. The third well region is formed under the first and second well regions in the semiconductor substrate in such a manner that a part of the third well region under the first well region is removed, thereby connecting the second well regions to one another electrically.Type: ApplicationFiled: November 30, 2007Publication date: March 27, 2008Applicant: KABUSHHIKI KAISHA TOSHIBAInventors: Takeshi SUGAHARA, Yasuhito Itaka
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Patent number: 7310616Abstract: In one embodiment the present invention relates to a method for structuring a transaction involving a first party having a long position in a security and a second party desiring to acquire short exposure to the security. In one example an agent or intermediary acts between the first party and the second party. In another example the first party and the second party deal directly with one another.Type: GrantFiled: February 1, 2002Date of Patent: December 18, 2007Assignee: Goldman Sachs & Co.Inventor: James Takeshi Sugahara
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Patent number: 7304884Abstract: A semiconductor memory device includes first and second bit lines, memory cells each including first and second storage nodes, which are connected through selecting transistors to the first and second bit lines, respectively, a pre-charge circuit configured to pre-charge the first and second bit lines to a predetermined potential so as to read data, a hold circuit configured to maintain a potential level of the first and second bit lines, a read circuit connected to the first bit line, and a leak circuit having one terminal connected to the second bit line and another terminal connected to a ground. The leak circuit allows a current to leak from the second bit line.Type: GrantFiled: August 8, 2006Date of Patent: December 4, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Sugahara, Yukihiro Fujimoto
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Patent number: 7236955Abstract: In one embodiment, a method for structuring a transaction between a first party having a long position in a security and a second party is provided. In another embodiment, a method for structuring a transaction involving a first party having a long position in a security, a second party acting as a transaction facilitator, and a third party desiring to acquire short exposure to the security is provided.Type: GrantFiled: June 15, 2001Date of Patent: June 26, 2007Assignee: Goldman Sachs & Co.Inventor: James Takeshi Sugahara
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Publication number: 20060268599Abstract: A semiconductor memory device includes first and second bit lines, memory cells each including first and second storage nodes, which are connected through selecting transistors to the first and second bit lines, respectively, a pre-charge circuit configured to pre-charge the first and second bit lines to a predetermined potential so as to read data, a hold circuit configured to maintain a potential level of the first and second bit lines, a read circuit connected to the first bit line, and a leak circuit having one terminal connected to the second bit line and another terminal connected to a ground. The leak circuit allows a current to leak from the second bit line.Type: ApplicationFiled: August 8, 2006Publication date: November 30, 2006Inventors: Takeshi Sugahara, Yukihiro Fujimoto
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Patent number: 7120076Abstract: There is disclosed a semiconductor memory device which comprises a plurality of bit line pairs each having first and second bit lines arranged in a first direction, a cell array having a plurality of SRAM cells each of which is connected between the first and second bit lines of a corresponding bit line pair via first and second storage nodes, respectively, a plurality of word lines arranged in a second direction crossing the first direction, and a data write circuit which, in the write mode, writes data into an SRAM cell selected by a word line via the first and second bit lines and, in the read mode, rewrites data read onto the first bit line from an SRAM cell selected by a word line onto the first bit line.Type: GrantFiled: December 1, 2003Date of Patent: October 10, 2006Assignee: Kabushiki Kaisha ToshibaInventor: Takeshi Sugahara
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Patent number: 7116574Abstract: A semiconductor memory device includes first and second bit lines, memory cells each including first and second storage nodes, which are connected through selecting transistors to the first and second bit lines, respectively, a pre-charge circuit configured to pre-charge the first and second bit lines to a predetermined potential so as to read data, a hold circuit configured to maintain a potential level of the first and second bit lines, a read circuit connected to the first bit line, and a leak circuit having one terminal connected to the second bit line and another terminal connected to a ground. The leak circuit allows a current to leak from the second bit line.Type: GrantFiled: August 12, 2004Date of Patent: October 3, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Sugahara, Yukihiro Fujimoto
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Publication number: 20060197110Abstract: In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the second conductivity type are formed. The second well regions are formed in the semiconductor substrate excluding the region where the first well region has been formed. The third well region is formed under the first and second well regions in the semiconductor substrate in such a manner that a part of the third well region under the first well region is removed, thereby connecting the second well regions to one another electrically.Type: ApplicationFiled: June 27, 2005Publication date: September 7, 2006Inventors: Takeshi Sugahara, Yasuhito Itaka