Abstract: A liquid crystal drive device includes a common driver configured to sequentially output a scanning signal having a plurality of voltage levels to a plurality of common wirings in a time division manner, a segment driver configured to output a display signal having a plurality of voltage levels to a plurality of segment wirings, and a contrast adjustment unit configured to generate contrast adjustment periods that are inserted into all duty periods, and output, to the common driver and the segment driver, a contrast control signal to control the timing of when the contrast adjustment periods are inserted into the duty periods in synchronization with the timing of the scanning signal and the display signal. The scanning signal and the display signal are output at an identical potential when a contrast adjustment period is indicated by the output of the contrast control signal.

Abstract: A liquid crystal drive device includes a common driver configured to sequentially output a scanning signal having a plurality of voltage levels to a plurality of common wirings in a time division manner, a segment driver configured to output a display signal having a plurality of voltage levels to a plurality of segment wirings, and a contrast adjustment unit configured to generate contrast adjustment periods that are inserted into all duty periods, and output, to the common driver and the segment driver, a contrast control signal to control the timing of when the contrast adjustment periods are inserted into the duty periods in synchronization with the timing of the scanning signal and the display signal. The scanning signal and the display signal are output at an identical potential when a contrast adjustment period is indicated by the output of the contrast control signal.

Abstract: A small chip size and high picture quality, and also a quick CPU access operation to memory are achieved for a semiconductor device for driving liquid crystals.

Abstract: A small chip size and high picture quality, and also a quick CPU access operation to memory are achieved for a semiconductor device for driving liquid crystals.

Abstract: Five voltage dividing resistors are connected in series between the nodes of external power supply voltages to obtain first to fourth divided voltages. A first power amplifier of an Ntop type for impedance conversion is connected to a node of the first voltage. A second power amplifier of a Ptop type for impedance conversion is connected to a node of the second voltage. A third power amplifier of the Ntop type for impedance conversion is connected to a node of the third voltage. A fourth power amplifier of the Ptop type for impedance conversion is connected to a node of the fourth voltage. In each of the first and third power amplifiers of the Ntop type, the ability of causing a current to flow out of the amplifier from the output terminal is set to be high, and the ability of causing a current to flow into the amplifier from the output terminal is set to be low.

Abstract: A gain stage and offset voltage elimination method. The gain stage includes an amplifier, condensers and a number of switches. The switches are arranged to discharge the condensers and then charge the condensors to the offset voltage during an initialize period. When an input voltage is applied to the gain stage, the condensers do not act as capacitive loads for the amplifier. The gain stage can thus more quickly charge the condensers since the charging speed is approximately equal to the slew rate of the amplifier. The period for initializing the gain stage can be shortened while minimizing the current consumed.

Abstract: A pen input liquid crystal display has row electrodes, column electrodes orthogonal to the row electrodes, and a liquid crystal layer interposed between the row and column electrodes. A pen input detecting signal is applied to one of the column electrodes, and display signals to the other column electrodes. The column electrode that receives the pen input detecting signal is sequentially shifted among the column electrodes, to simultaneously carry out a pen input scanning operation and an image displaying operation.

Abstract: A level shifting circuit has a high-level shifter connected to a first high voltage and to a first low voltage, for amplifying the peak voltage of an input signal; a low-level shifter connected to a second high voltage lower than the first high voltage and to a second low voltage lower than the first low voltage, for amplifying the trough voltage of the input signal; a high-voltage controlling transistor connected to the first high voltage and to an output node and turned on and off according to the output of the high-level shifter; and a low-voltage controlling transistor connected to the output node and to the second low voltage and turned on and off according to the output of the low-level shifter complementarily to the high-voltage controlling transistor. The level shifting circuit is capable of amplifying both the peak and trough voltages of an input signal.

Abstract: A P-well region is provided in a semiconductor substrate of N-type. A P-channel MOSFET is arranged in the N-type substrate while an N-channel MOSFET is arranged in the P-well region. The drain regions of the respective MOSFETs consist of high concentration impurity diffused regions and low concentration impurity diffused regions arranged about the respective high concentration impurity diffused regions. Also, a drain electrode is provided to cover the entire of the high and low concentration impurity diffused regions.