Patents by Inventor Takeshi Takanashi

Takeshi Takanashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100138466
    Abstract: Provided is a filter coefficient calculation method that calculates filter functions, each having (2n+1) rows and (2n+1) columns (n is an integer), the method including calculating a first filter function in accordance with a set value that is externally input, calculating an error between a total sum of values included in the first filter function and an ideal value of the total sum, supplying an odd error included in the error to a first origin coefficient that is located at a center of the first filter function as a first correction value if the error is an odd number, and supplying an even error to one of the first origin coefficient and a coefficient pair that is located symmetrically with respect to a point of the first origin coefficient as a second correction value, the even error being the error except the odd error.
    Type: Application
    Filed: November 25, 2009
    Publication date: June 3, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Ryoji Yanase, Takeshi Takanashi, Koichiro Suzuki
  • Patent number: 6253357
    Abstract: A method of arranging/wiring a core used to constitute a semiconductor device on a semiconductor chip includes a providing step, a step of arranging a core wiring line, a first performing step, a step of arranging the core, a making step and a second performing step. The providing step includes providing the core. The step of arranging the core wiring line includes arranging the core wiring line on the core. The first performing step includes performing a core operation check to the core on which the core wiring line is arranged. The step of arranging the core includes arranging the core to which the core operation check has been performed, on a semiconductor chip to produce an arranged core. The making step includes making a first wiring line capacitance of the core wiring line of the arranged core equal to a second wiring line capacitance of the core wiring line of the core when the core operation check of the core is performed.
    Type: Grant
    Filed: March 4, 1999
    Date of Patent: June 26, 2001
    Assignee: NEC Corporation
    Inventor: Takeshi Takanashi