Patents by Inventor Takeshi Tanaka

Takeshi Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10468992
    Abstract: An auxiliary power supply device includes: a resonance-type inverter circuit to convert DC power input from a DC power supply to AC power, a primary coil for input of AC power from the inverter circuit, a transformer for output of AC power from a secondary coil insulated from the primary coil, a converter circuit for conversion of AC power from the transformer to DC power, a filter condenser for smoothing of DC voltage from the converter circuit, and an inverter controller for output of a gate signal for causing operation of switching elements of the inverter circuit. The inverter controller, in a charging mode for charging the filter condenser, makes pulse width of the gate signal smaller than when in a running mode for running of electric rolling stock, and gradually increases the pulse width in accordance with an elapsed time under control in the charging mode.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: November 5, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takeshi Tanaka, Takeshi Yamamoto, Naoki Kuraba
  • Patent number: 10455246
    Abstract: An image coding method for improving coding efficiency by using more appropriate probability information is provided. The image coding method includes: a first coding step of coding a first set of blocks included in a first region sequentially based on first probability information; and a second coding step of coding a second set of blocks included in a second region sequentially based on second probability information. In the first coding step, the first probability information is updated depending on data of a target block to be coded, after coding the target block and before coding a next target block. In the second coding step, the second probability information is updated depending on the first probability information updated in the first coding step, before coding the first target block.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: October 22, 2019
    Assignee: SUN PATENT TRUST
    Inventors: Takeshi Tanaka, Hisao Sasai
  • Patent number: 10444298
    Abstract: There is provided a magnetic noise rejection apparatus which includes: a plurality of cancellation coils arranged near a target object; a plurality of magnetic sensors disposed inside the respective cancellation coils; an adder circuit configured to take a sum of outputs of the plurality of magnetic sensors; and a feedback control circuit configured to supply the cancellation coils with such a common feedback drive current that the sum of the outputs of the magnetic sensors is equal to a sum of outputs of the magnetic sensors under a zero magnetic field.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: October 15, 2019
    Assignee: ADVANTEST CORPORATION
    Inventors: Yoshiyuki Hata, Yuji Ogata, Takeshi Tanaka, Toshiaki Hayakawa
  • Patent number: 10433605
    Abstract: An acrylic fiber for artificial hair includes an acrylic polymer, wherein the acrylic polymer includes 29.5 to 79.5% by mass of acrylonitrile, 20 to 70% by mass of vinyl chloride and/or vinylidene chloride, and 0.5 to 5% by mass of a vinyl monomer comprising a sulfonic acid group. The acrylic fiber for artificial hair includes 0.3 to 2% by mass of a good solvent for the acrylic polymer and 0.1 to 5% by mass of a compound comprising an epoxy group.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: October 8, 2019
    Assignee: KANEKA CORPORATION
    Inventors: Takeshi Tanaka, Akihiro Okamoto, Tomomichi Hashimoto, Sota Okumura
  • Patent number: 10340345
    Abstract: A nitride semiconductor epitaxial wafer includes a substrate, a GaN layer provided over the substrate, and an AlGaN layer provided over the GaN layer. The GaN layer has a wurtzite crystal structure, and a ratio c/a of a lattice constant c in a c-axis orientation of the GaN layer to a lattice constant a in an a-axis orientation of the GaN layer is not more than 1.6266.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: July 2, 2019
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Takeshi Tanaka, Naoki Kaneda, Yoshinobu Narita
  • Patent number: 10312227
    Abstract: First and second element pairs formed by connecting FWDs and MOSFETs in antiparallel are connected in series and sealed by resin to configure a core module. In the core module, a first drain electrode, a first source electrode, a second drain electrode, and a second source electrode are exposed to the surface. A cover with terminals is put on the core module. At this time, each of the direct-current positive electrode terminal, the direct-current negative electrode terminal, and the alternating-current terminal of the cover with terminals is electrically connected to each of the first drain electrode, the second source electrode, and the first source electrode and the second drain electrode.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: June 4, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yukio Nakashima, Takeshi Tanaka
  • Publication number: 20190149148
    Abstract: A switching circuit includes: a drive power supply; a first transistor and a second transistor; a drive signal source; and a drive circuit. Each of the first transistor and the second transistor includes: a drain electrode and a source electrode in which a main current flows when a corresponding one of the first transistor and the second transistor is ON; a first source terminal for passing the main current; and a second source terminal. Here, the first source terminal is connected to the source electrode at an impedance lower than an impedance of the second source terminal.
    Type: Application
    Filed: December 19, 2018
    Publication date: May 16, 2019
    Inventors: Takahiro UEHARA, Takuya ISHII, Hiroyuki HANDA, Atsushi KITAGAWA, Takeshi TANAKA
  • Publication number: 20190075313
    Abstract: An image coding method for improving coding efficiency by using more appropriate probability information is provided. The image coding method includes: a first coding step of coding a first set of blocks included in a first region sequentially based on first probability information; and a second coding step of coding a second set of blocks included in a second region sequentially based on second probability information. In the first coding step, the first probability information is updated depending on data of a target block to be coded, after coding the target block and before coding a next target block. In the second coding step, the second probability information is updated depending on the first probability information updated in the first coding step, before coding the first target block.
    Type: Application
    Filed: November 5, 2018
    Publication date: March 7, 2019
    Inventors: Takeshi TANAKA, Hisao SASAI
  • Patent number: 10205449
    Abstract: A switching circuit includes: a drive power supply; a first transistor and a second transistor; a drive signal source; and a drive circuit. Each of the first transistor and the second transistor includes: a drain electrode and a source electrode in which a main current flows when a corresponding one of the first transistor and the second transistor is ON; a first source terminal for passing the main current; and a second source terminal. Here, the first source terminal is connected to the source electrode at an impedance lower than an impedance of the second source terminal.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: February 12, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takahiro Uehara, Takuya Ishii, Hiroyuki Handa, Atsushi Kitagawa, Takeshi Tanaka
  • Publication number: 20190021425
    Abstract: Modacrylic fibers for artificial hair include a modacrylic polymer; and a condensed phosphate. The modacrylic polymer includes 29.5 to 79.5% by mass of acrylonitrile, 20 to 70% by mass of vinyl chloride and/or vinylidene chloride, and 0.5 to 5% by mass of a sulfonic acid group containing vinyl monomer, with respect to a total mass of the modacrylic polymer. A content of the condensed phosphate in the modacrylic fibers is 0.05 to 0.57% by mass.
    Type: Application
    Filed: September 20, 2018
    Publication date: January 24, 2019
    Applicant: KANEKA CORPORATION
    Inventors: Takeshi Tanaka, Sota Okumura, Tomomichi Hashimoto
  • Publication number: 20190019785
    Abstract: First and second element pairs formed by connecting FWDs and MOSFETs in antiparallel are connected in series and sealed by resin to configure a core module. In the core module, a first drain electrode, a first source electrode, a second drain electrode, and a second source electrode are exposed to the surface. A cover with terminals is put on the core module. At this time, each of the direct-current positive electrode terminal, the direct-current negative electrode terminal, and the alternating-current terminal of the cover with terminals is electrically connected to each of the first drain electrode, the second source electrode, and the first source electrode and the second drain electrode.
    Type: Application
    Filed: February 18, 2016
    Publication date: January 17, 2019
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yukio Nakashima, Takeshi Tanaka
  • Publication number: 20190016143
    Abstract: A liquid ejecting apparatus includes a liquid ejecting head which ejects a liquid, a discharge portion which discharges a waste liquid discharged from the liquid ejecting head, and a mounting unit which is provided with the discharge portion and in which is mounted a waste liquid container capable of storing the waste liquid which is discharged from the discharge portion, in which the mounting unit includes a liquid holding portion capable of holding the waste liquid in a periphery of the discharge portion.
    Type: Application
    Filed: July 11, 2018
    Publication date: January 17, 2019
    Inventors: Toshiyuki OCHIAI, Tsutomu KOBAYASHI, Takeshi TANAKA
  • Patent number: 10171827
    Abstract: An image coding method for improving coding efficiency by using more appropriate probability information is provided. The image coding method includes: a first coding step of coding a first set of blocks included in a first region sequentially based on first probability information; and a second coding step of coding a second set of blocks included in a second region sequentially based on second probability information. In the first coding step, the first probability information is updated depending on data of a target block to be coded, after coding the target block and before coding a next target block. In the second coding step, the second probability information is updated depending on the first probability information updated in the first coding step, before coding the first target block.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: January 1, 2019
    Assignee: SUN PATENT TRUST
    Inventors: Takeshi Tanaka, Hisao Sasai
  • Publication number: 20180366572
    Abstract: There is provided a nitride semiconductor epitaxial substrate, including: a substrate; a first nitride semiconductor layer formed on the substrate, as an electron transit layer in which two-dimensional electron gas exists; and a second nitride semiconductor layer formed on the first nitride semiconductor layer, as an electron supply layer, wherein the second nitride semiconductor layer includes a portion in which a hydrogen concentration is higher than that of the first nitride semiconductor layer and a difference of the hydrogen concentration from that of the first nitride semiconductor layer is 2×1018 cm?3 or less.
    Type: Application
    Filed: June 18, 2018
    Publication date: December 20, 2018
    Inventor: Takeshi TANAKA
  • Publication number: 20180321884
    Abstract: According to one embodiment, a memory system includes a controller. The controller controls throttling to make a performance value of the memory system fall between a first performance value and a second performance value. The throttling limits the number of times of accesses per unit time to a nonvolatile memory. The first performance value is calculated based on a third performance value of the memory system and is greater than the third performance value. The third performance value is a value which is expected to be reached at a time when a first period has elapsed since the memory system started being used if throttling is not performed. The second performance value is provided between the first performance value and the third performance value.
    Type: Application
    Filed: July 11, 2018
    Publication date: November 8, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Takeshi TANAKA, Kenichi Iwai, Maoko Oyamada
  • Publication number: 20180310353
    Abstract: There is provided a communicating, at a first network access point, with a core network entity using a user plane protocol, said communicating comprising receiving user data from the core network entity on a first bearer, the first bearer capable of being split with a second network access point such that at least some of the user data is provided to the second network access point, the first network access point and the second network access point configured to communicate wirelessly with a plurality of user equipments, and wherein the first network access point does not communicate with the core network using a control plane protocol associated with the first bearer.
    Type: Application
    Filed: June 20, 2016
    Publication date: October 25, 2018
    Inventors: Sheshachalam BANGALORE SATYANARAYANA, Tsunehiko CHIBA, Suresh KALYANASUNDARAM, Masatoshi NAKAMATA, Claudio ROSA, Takeshi TANAKA
  • Patent number: 10037172
    Abstract: According to one embodiment, a memory system includes a controller. The controller controls throttling to make a performance value of the memory system fall between a first performance value and a second performance value. The throttling limits the number of times of accesses per unit time to a nonvolatile memory. The first performance value is calculated based on a third performance value of the memory system and is greater than the third performance value. The third performance value is a value which is expected to be reached at a time when a first period has elapsed since the memory system started being used if throttling is not performed. The second performance value is provided between the first performance value and the third performance value.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: July 31, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takeshi Tanaka, Kenichi Iwai, Maoko Oyamada
  • Publication number: 20180212509
    Abstract: A switching circuit includes: a drive power supply; a first transistor and a second transistor; a drive signal source; and a drive circuit. Each of the first transistor and the second transistor includes: a drain electrode and a source electrode in which a main current flows when a corresponding one of the first transistor and the second transistor is ON; a first source terminal for passing the main current; and a second source terminal. Here, the first source terminal is connected to the source electrode at an impedance lower than an impedance of the second source terminal.
    Type: Application
    Filed: March 19, 2018
    Publication date: July 26, 2018
    Inventors: Takahiro UEHARA, Takuya ISHII, Hiroyuki HANDA, Atsushi KITAGAWA, Takeshi TANAKA
  • Patent number: 10033997
    Abstract: An image decoding device is provided that decodes, without an increase in the circuit size, a coded video sequence including a large-size block. The image decoding apparatus includes: a block division unit which divides a current block that is to be decoded and is included in a picture of the coded video sequence, into sub-blocks; an image obtainment unit which obtains, for each of the sub-blocks, image data corresponding to the sub-block from a recording medium; a prediction unit which generates, for each of the sub-blocks, a predicted image of the sub-block, based on the image data obtained by the image obtainment unit; and a reconstruction unit which reconstructs each of the sub-blocks, by adding the predicted image generated for the sub-block to the sub-block.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: July 24, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yoshiteru Hayashi, Takeshi Tanaka, Takashi Hashimoto, Satoshi Kajita, Hiroshi Amano
  • Patent number: 10020653
    Abstract: The station-building power supply device includes a capacitor unit that stores therein surplus regenerative power, a first power conversion unit that performs DC/DC power conversion, and a second power conversion unit that converts DC power. A first voltage threshold for detecting the occurrence of surplus regenerative power is set and a first SOC threshold for detecting whether the capacitor unit can discharge is set. The first power conversion unit is controlled such that power is supplied from the feeder to the capacitor unit to charge the capacitor unit when the feeding voltage exceeds the first voltage threshold, and the second power conversion unit is controlled such that power is supplied from the capacitor unit to the station loads when the SOC of the capacitor unit exceeds the first SOC threshold.
    Type: Grant
    Filed: November 28, 2013
    Date of Patent: July 10, 2018
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasushi Matsumura, Takeshi Tanaka, Wataru Okuda, Shuji Ishikura