Patents by Inventor Takeshi Tawara

Takeshi Tawara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11948976
    Abstract: A vertical metal oxide semiconductor field effect transistor, including a starting substrate of a first conductivity type, a second first-conductivity-type epitaxial layer provided on a first surface of the starting substrate via a first first-conductivity-type epitaxial layer, a first semiconductor region of the first conductivity type provided as a portion of the second first-conductivity-type epitaxial layer, a second-conductivity-type epitaxial layer forming a pn junction interface with the second first-conductivity-type epitaxial layer and supplying a minority carrier to the second first-conductivity-type epitaxial layer, a plurality of second semiconductor regions of the first conductivity type selectively provided in the second-conductivity-type epitaxial layer, a plurality of trenches penetrating through the second semiconductor regions and the second-conductivity-type epitaxial layer, and a plurality of gate electrodes provided in the trenches via gate insulating films.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: April 2, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Tawara, Hidekazu Tsuchida, Koichi Murata
  • Publication number: 20240038851
    Abstract: A silicon carbide semiconductor device has an n-type silicon carbide semiconductor substrate, an n-type first semiconductor layer, n-type first JFET regions, a p-type second semiconductor layer, n-type first semiconductor regions, and trenches. The first semiconductor layer has an impurity concentration lower than that of the substrate. The first JFET regions are provided in a surface layer of the first semiconductor layer and have an effective donor concentration higher than that of the first semiconductor. The p-type second semiconductor layer is provided at a surface of the first semiconductor layer. The n-type first semiconductor regions are selectively provided in a surface layer of the second semiconductor layer. The trenches penetrate through the first semiconductor regions, the second semiconductor layer, and the first JFET regions. The first JFET regions are doped with an acceptor that is aluminum and a donor that is nitrogen or phosphorus.
    Type: Application
    Filed: September 28, 2023
    Publication date: February 1, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi TAWARA, Shinsuke HARADA
  • Publication number: 20230100453
    Abstract: An n--type drift layer is an n--type epitaxial layer doped with nitrogen as an n-type dopant and is co-doped with aluminum as a p-type dopant, the n--type drift layer containing the nitrogen and aluminum substantially uniformly throughout. An n-type impurity concentration of the n--type drift layer is an impurity concentration determined by subtracting the aluminum concentration from the nitrogen concentration of the n--type drift layer; a predetermined blocking voltage is realized by the impurity concentration. A combined impurity concentration of the nitrogen and aluminum of the n--type drift layer is at least 3×1016/cm3.
    Type: Application
    Filed: November 29, 2022
    Publication date: March 30, 2023
    Applicants: FUJI ELECTRIC CO., LTD., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Takeshi TAWARA, Shinsuke HARADA
  • Publication number: 20220285489
    Abstract: A method of manufacturing a superjunction silicon carbide semiconductor device is provided, enabling a reduction of the number of times a combination of epitaxial growth and ion implantation for forming a parallel pn structure is performed. In the method of manufacturing the superjunction silicon carbide semiconductor device, forming an epitaxial layer 2a, 2b of a second conductivity type on a front surface of a silicon carbide semiconductor substrate 1 of a first conductivity type and selectively forming semiconductor regions 4a, 4b of the first conductivity type by implanting nitrogen ions in the epitaxial layer are repeated multiple times, thereby forming the parallel pn structure.
    Type: Application
    Filed: March 3, 2022
    Publication date: September 8, 2022
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Kensuke TAKENAKA, Takeshi TAWARA, Shinsuke HARADA
  • Publication number: 20220190114
    Abstract: A vertical metal oxide semiconductor field effect transistor, including a starting substrate of a first conductivity type, a second first-conductivity-type epitaxial layer provided on a first surface of the starting substrate via a first first-conductivity-type epitaxial layer, a first semiconductor region of the first conductivity type provided as a portion of the second first-conductivity-type epitaxial layer, a second-conductivity-type epitaxial layer forming a pn junction interface with the second first-conductivity-type epitaxial layer and supplying a minority carrier to the second first-conductivity-type epitaxial layer, a plurality of second semiconductor regions of the first conductivity type selectively provided in the second-conductivity-type epitaxial layer, a plurality of trenches penetrating through the second semiconductor regions and the second-conductivity-type epitaxial layer, and a plurality of gate electrodes provided in the trenches via gate insulating films.
    Type: Application
    Filed: October 29, 2021
    Publication date: June 16, 2022
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi TAWARA, Hidekazu TSUCHIDA, Koichi MURATA
  • Publication number: 20220123112
    Abstract: A silicon carbide semiconductor device has an active region and a termination structure portion disposed outside of the active region. The silicon carbide semiconductor device includes a semiconductor substrate of a second conductivity type, a first semiconductor layer of the second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, a gate insulating film, a gate electrode, a first electrode, and a second electrode. During bipolar operation, a smaller density among an electron density and a hole density of an end of the second semiconductor layer in the termination structure portion is at most 1×1015/cm3.
    Type: Application
    Filed: November 30, 2021
    Publication date: April 21, 2022
    Applicants: FUJI ELECTRIC CO., LTD., MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takeshi TAWARA, Tomonori MIZUSHIMA, Shinichiro MATSUNAGA, Kensuke TAKENAKA, Manabu TAKEI, Hidekazu TSUCHIDA, Kouichi MURATA, Akihiro KOYAMA, Koji NAKAYAMA, Mitsuru SOMETANI, Yoshiyuki YONEZAWA, Yuji KIUCHI
  • Patent number: 11296192
    Abstract: A silicon carbide semiconductor device includes, sequentially, a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type provided on the first semiconductor layer, a third semiconductor layer of the first conductivity type provided on the second semiconductor layer, and a fourth semiconductor layer of a second conductivity type provided on the third semiconductor layer. A first electrode is provided on the first semiconductor layer, and a second electrode is provided on the fourth semiconductor layer. An impurity concentration of the second semiconductor layer is higher than that of the first semiconductor layer, and an impurity concentration of the third semiconductor layer is lower than that of the second semiconductor layer.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: April 5, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Tawara, Mina Ohse
  • Patent number: 11201218
    Abstract: A silicon carbide epitaxial substrate including a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, and a high-density foreign element region. The first semiconductor layer is provided at a front surface of the silicon carbide semiconductor substrate and has an impurity concentration lower than that of the silicon carbide semiconductor substrate. The high-density foreign element region is provided in the silicon carbide semiconductor substrate at a predetermined depth from the front surface thereof. The high-density foreign element region contains an element other than carbon and silicon, at a density higher than that of the silicon carbide semiconductor substrate.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: December 14, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeshi Tawara
  • Patent number: 10868122
    Abstract: During epitaxial growth of an n?-type drift layer having a uniform nitrogen concentration, vanadium is doped in addition to the nitrogen, whereby an n?-type lifetime reduced layer is selectively formed in the n?-type drift layer. The n?-type lifetime reduced layer is disposed at a depth that is more than 5 ?m from a pn junction surface between a p-type anode layer and the n?-type drift layer in a direction toward a cathode side, and the n?-type lifetime reduced layer is disposed separated from the pn junction surface. Further, the n?-type lifetime reduced layer is disposed in a range from the pn junction surface to a depth that is ? times a thickness of the n?-type drift layer. A vanadium concentration of the n?-type lifetime reduced layer is 1/100 to ? of a nitrogen concentration of the n?-type lifetime reduced layer.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: December 15, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Tawara, Koji Nakayama, Yoshiyuki Yonezawa, Hidekazu Tsuchida, Koichi Murata
  • Patent number: 10796906
    Abstract: A silicon carbide semiconductor substrate includes a silicon carbide substrate of a first conductivity type, an epitaxial layer of the first conductivity type provided on a front surface of the silicon carbide substrate, an impurity concentration of the epitaxial layer being 1×1017/cm3 to 1×1018/cm3, and a film thickness of the epitaxial layer being 1 ?m to 5 ?m. The silicon carbide semiconductor substrate further includes a buffer layer of the first conductivity type provided on a surface of a first side of the epitaxial layer opposite a second side facing the silicon carbide substrate, an impurity concentration of the buffer layer being about a same as that of the silicon carbide substrate, and a drift layer of the first conductivity type provided on a surface of a first side of the buffer layer opposite a second side facing toward the silicon carbide substrate, an impurity concentration of the drift layer being lower than that of the buffer layer.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: October 6, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeshi Tawara
  • Publication number: 20200312966
    Abstract: A silicon carbide epitaxial substrate including a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, and a high-density foreign element region. The first semiconductor layer is provided at a front surface of the silicon carbide semiconductor substrate and has an impurity concentration lower than that of the silicon carbide semiconductor substrate. The high-density foreign element region is provided in the silicon carbide semiconductor substrate at a predetermined depth from the front surface thereof. The high-density foreign element region contains an element other than carbon and silicon, at a density higher than that of the silicon carbide semiconductor substrate.
    Type: Application
    Filed: March 10, 2020
    Publication date: October 1, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Takeshi TAWARA
  • Patent number: 10748763
    Abstract: An n?-type epitaxial layer is grown on a front surface of the silicon carbide substrate by a CVD method in a mixed gas atmosphere containing a source gas, a carrier gas, a doping gas, an additive gas, and a gas containing vanadium. The doping gas is nitrogen gas; and the gas containing vanadium is vanadium tetrachloride gas. In the mixed gas atmosphere, the vanadium bonds with the nitrogen, producing vanadium nitride, whereby the nitrogen concentration in the mixed gas atmosphere substantially decreases. As a result, the nitrogen taken in by the n?-type epitaxial layer decreases and the n?-type epitaxial layer including nitrogen and vanadium as dopants is grown having a low impurity concentration.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: August 18, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Tawara, Hidekazu Tsuchida, Tetsuya Miyazawa
  • Publication number: 20200251333
    Abstract: A silicon carbide semiconductor substrate includes a silicon carbide substrate of a first conductivity type, an epitaxial layer of the first conductivity type provided on a front surface of the silicon carbide substrate, an impurity concentration of the epitaxial layer being 1×1017/cm3 to 1×1018/cm3, and a film thickness of the epitaxial layer being 1 ?m to 5 ?m. The silicon carbide semiconductor substrate further includes a buffer layer of the first conductivity type provided on a surface of a first side of the epitaxial layer opposite a second side facing the silicon carbide substrate, an impurity concentration of the buffer layer being about a same as that of the silicon carbide substrate, and a drift layer of the first conductivity type provided on a surface of a first side of the buffer layer opposite a second side facing toward the silicon carbide substrate, an impurity concentration of the drift layer being lower than that of the buffer layer.
    Type: Application
    Filed: April 20, 2020
    Publication date: August 6, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Takeshi Tawara
  • Patent number: 10665681
    Abstract: On a front surface of an n+-type starting substrate containing silicon carbide, a pin diode is configured having silicon carbide layers constituting an n+-type buffer layer, an n?-type drift layer, and a p+-type anode layer sequentially formed by epitaxial growth. The n+-type buffer layer is formed by so-called co-doping of nitrogen and vanadium, which forms a recombination center, together with an n-type impurity. The n+-type buffer layer includes a first part disposed at a side of a second interface of the buffer layer with the substrate and a second part disposed at side of a first interface of the buffer layer with the drift layer. The vanadium concentration in the second part is lower than that in the first part. The vanadium concentration in the second part is at most one tenth of the maximum value Vmax of the vanadium concentration in the n+-type buffer layer.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: May 26, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Tawara, Hidekazu Tsuchida, Koichi Murata
  • Publication number: 20200144371
    Abstract: A silicon carbide semiconductor device includes, sequentially, a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type provided on the first semiconductor layer, a third semiconductor layer of the first conductivity type provided on the second semiconductor layer, and a fourth semiconductor layer of a second conductivity type provided on the third semiconductor layer. A first electrode is provided on the first semiconductor layer, and a second electrode is provided on the fourth semiconductor layer. An impurity concentration of the second semiconductor layer is higher than that of the first semiconductor layer, and an impurity concentration of the third semiconductor layer is lower than that of the second semiconductor layer.
    Type: Application
    Filed: October 23, 2019
    Publication date: May 7, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi TAWARA, Mina OHSE
  • Patent number: 10629432
    Abstract: A silicon carbide semiconductor substrate includes a silicon carbide substrate of a first conductivity type, an epitaxial layer of the first conductivity type provided on a front surface of the silicon carbide substrate, an impurity concentration of the epitaxial layer being 1×1017/cm3 to 1×1018/cm3, and a film thickness of the epitaxial layer being 1 ?m to 5 ?m. The silicon carbide semiconductor substrate further includes a buffer layer of the first conductivity type provided on a surface of a first side of the epitaxial layer opposite a second side facing the silicon carbide substrate, an impurity concentration of the buffer layer being about a same as that of the silicon carbide substrate, and a drift layer of the first conductivity type provided on a surface of a first side of the buffer layer opposite a second side facing toward the silicon carbide substrate, an impurity concentration of the drift layer being lower than that of the buffer layer.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: April 21, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeshi Tawara
  • Patent number: 10573716
    Abstract: A silicon carbide semiconductor device, including a silicon carbide semiconductor substrate of a first conductivity type, a first silicon carbide semiconductor deposition layer of the first conductivity type, deposited on a front surface of the silicon carbide semiconductor substrate and having an impurity concentration that is lower than that of the silicon carbide semiconductor substrate, a base region of a second conductivity type, selectively provided in the first silicon carbide semiconductor deposition layer at a front surface thereof, and a second silicon carbide semiconductor deposition layer of the second conductivity type, deposited on the front surface of the first silicon carbide semiconductor deposition layer. The base region has an impurity concentration of 1×1018 to 1×1020/cm3 and a thickness of 0.3 to 1.0 ?m. The second silicon carbide semiconductor deposition layer has a surface defect density of 3 defects/cm2.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: February 25, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeshi Tawara
  • Patent number: 10522667
    Abstract: The SiC-IGBT includes a p-type collector layer, an n?-type voltage-blocking-layer provided on the collector layer, p-type base regions provided on the n?-type voltage-blocking-layer, n+-type emitter regions provided in an upper portion of the p-type base region, a gate insulating film provided in an upper portion of the voltage-blocking-layer, and a gate electrode provided on the gate insulating film. The p-type buffer layer has thickness of five micrometers or more and 20 micrometers or less and is doped with Al at impurity concentration of 5×1017 cm?3 or more and 5×1018 cm?3 or less and doped with B at impurity concentration of 2×1016 cm?3 or more and less than 5×1017 cm?3.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: December 31, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Tawara, Hidekazu Tsuchida, Koichi Murata
  • Publication number: 20190393312
    Abstract: During epitaxial growth of an n?-type drift layer having a uniform nitrogen concentration, vanadium is doped in addition to the nitrogen, whereby an n?-type lifetime reduced layer is selectively formed in the n?-type drift layer. The n?-type lifetime reduced layer is disposed at a depth that is more than 5 ?m from a pn junction surface between a p-type anode layer and the n?-type drift layer in a direction toward a cathode side, and the n?-type lifetime reduced layer is disposed separated from the pn junction surface. Further, the n?-type lifetime reduced layer is disposed in a range from the pn junction surface to a depth that is ? times a thickness of the n?-type drift layer. A vanadium concentration of the n?-type lifetime reduced layer is 1/100 to ? of a nitrogen concentration of the n?-type lifetime reduced layer.
    Type: Application
    Filed: May 31, 2019
    Publication date: December 26, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi TAWARA, Koji Nakayama, Yoshiyuki Yonezawa, Hidekazu Tsuchida, Koichi Murata
  • Patent number: 10453924
    Abstract: A silicon carbide semiconductor substrate, including a silicon carbide substrate of a first conductivity type, a buffer layer of the first conductivity type and an epitaxial layer of the first conductivity type. The silicon carbide substrate has a central part and a peripheral part surrounding the central part, and is doped with a first impurity that determines the first conductivity type. The buffer layer is provided on a front surface of the central part of the silicon carbide substrate, and is doped with the first impurity, of which a concentration is at least 1.0×1018/cm3, and a second impurity different from the first impurity. The epitaxial layer is provided on a front surface of the peripheral part of the silicon carbide substrate, and is doped with the first impurity, of which a concentration is lower than the concentration of the first impurity in the buffer layer.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: October 22, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Tawara, Hidekazu Tsuchida, Tetsuya Miyazawa