Abstract: A transmission device performing prescribed processing on signals of a plurality of channels and transmitting the signals of the plurality of channels. The device includes a first storage unit for storing, in different memory cells for each channel, first control data in which one or more types of control data elements for each channel are configured as at least one word data; a first data structure conversion unit for selecting control data elements of the same type from the first control data of the plurality of channels stored in the first storage unit, and converting the structure of the first control data such that the control data elements of the same type are configured as one word data; and a data generation unit for processing, in word units, the first control data after conversion by the first data structure conversion unit, and generating second control data necessary for the prescribed processing.

Abstract: A method includes steps of calculating, for each predetermined operation included in a program, an execution time required when the operation is executed by a predetermined processor, or calculating, for each predetermined operation included in the program, a circuit size required when the operation is realized in a form of hardware according to a predetermined technology; and calculating, for the entirety of the predetermined program or operations corresponding to a part the entirety of the predetermined program, a total execution time required when the entirety of the predetermined program is executed by the predetermined processor, as a result of applying in sequence the required execution time, or calculating, for the entirety of the predetermined program or operations corresponding to a part the entirety of the predetermined program, a total circuit size required when the entirety of the predetermined program or programs corresponding to a part of the entirety of the predetermined program, as a result of

Abstract: A method includes steps of calculating, for each predetermined operation included in a program, an execution time required when the operation is executed by a predetermined processor, or calculating, for each predetermined operation included in the program, a circuit size required when the operation is realized in a form of hardware according to a predetermined technology; and calculating, for the entirety of the predetermined program or operations corresponding to a part the entirety of the predetermined program, a total execution time required when the entirety of the predetermined program is executed by the predetermined processor, as a result of applying in sequence the required execution time, or calculating, for the entirety of the predetermined program or operations corresponding to a part the entirety of the predetermined program, a total circuit size required when the entirety of the predetermined program or programs corresponding to a part of the entirety of the predetermined program, as a result of

Abstract: A data control device capable of high-quality, high-efficiency control for speeding up data processing, thus permitting improvement of the throughput of a system. Attribute analyzing unit analyzes an attribute of data, and a main memory stores setting information of the data in a region corresponding to the attribute. A highway cache memory stores the data, and also receives and transmits the data on a highway. A processor performs an operation on the data in accordance with the setting information. A data cache memory is interposed between the processor and the main memory and stores the setting information.

Abstract: A communication protocol processing unit by a multiprocessor is disclosed, and includes a first processor for performing a process demanding a real time property on a stream of communication data; and a second processor for performing a process not demanding the real time property, wherein the first processor transfers using parameters paired with the communication data to be processed to the second processor, and the second processor is structured so as to refer to the transferred communication data and parameters to process.

Abstract: The present invention provides a transmission device performing prescribed processing on signals of a plurality of channels and transmitting the signals of the plurality of channels, comprising: a first storage unit for storing, in different memory cells for each channel, first control data in which one or more types of control data elements for each channel are configured as at least one word data; a first data structure conversion unit for selecting control data elements of the same type from said first control data of the plurality of channels stored in said first storage unit, and converting the structure of said first control data such that the control data elements of the same type are configured as one word data; and a data generation unit for processing, in word units, said first control data after conversion by said first data structure conversion unit, and generating second control data necessary for said prescribed processing.

Abstract: A data control device capable of high-quality, high-efficiency control for speeding up data processing, thus permitting improvement of the throughput of a system. Attribute analyzing unit analyzes an attribute of data, and a main memory stores setting information of the data in a region corresponding to the attribute. A highway cache memory stores the data, and also receives and transmits the data on a highway. A processor performs an operation on the data in accordance with the setting information. A data cache memory is interposed between the processor and the main memory and stores the setting information.

Abstract: In an ATM communication monitoring device which monitors by using a monitor timer, a connection ID generator generates connection ID's, and an OAM cell generator queues connection information of an OAM cell to be generated corresponding to the connection ID's at a predetermined cycle where the fundamental cycle signal is counted and generates the OAM cell, in order to increase operation time accuracy of the monitor timer and reduce the hardware cost. Also, a counter counts the fundamental cycle signal, and an OAM cell generator queues connection information of an OAM cell corresponding to the connection ID's at a predetermined cycle based on a value of the counter and generates the OAM cell.

Abstract: A communication protocol processing unit by a multiprocessor is disclosed, and includes a first processor for performing a process demanding a real time property on a stream of communication data; and a second processor for performing a process not demanding the real time property, wherein the first processor transfers using parameters paired with the communication data to be processed to the second processor, and the second processor is structured so as to refer to the transferred communication data and parameters to process.

Abstract: A memory access system includes a memory, a processor unit, and a memory interface unit. The processor unit includes an operation-request generating unit and an operation-request sending unit. The operation-request generating unit generates an operation request for an operation which is to be performed on the data stored in the memory, and the operation-request sending unit sends the operation request to a memory interface unit. The memory interface unit includes an operation-request storing unit, an operation performing unit, and an operation-result sending unit. The operation-request storing unit receives and stores the operation request. The operation performing unit operates independently of the processor unit so as to access the memory based on the operation request, and perform the operation on the data. The operation-result sending unit sends a result of the operation to the processor unit.

Abstract: A pointer processing apparatus in an SDH transmission system used to serially conducting a pointer process on inputted multiplex data has an address generating unit for allocating an address to each channel of the multiplex data, a RAM for holding an information group obtained by a pointer extracting process and a pointer process, and RAM controlling unit for controlling a sequence of an operation to write-in/read-out the RAM to serially conduct the pointer process on the received multiplex data, thereby largely decreasing the circuit scale, the power consumption, the number of distributions and the like. A POH terminating operation process is conducted in a POH terminating operation process unit, and an obtained result of the POH terminating operation is stored in a storage area for a corresponding channel of a storage unit, whereby the POH terminating operation process can be conducted without separating a multiplex signal into channels.