Patents by Inventor Takeshi Uchihara

Takeshi Uchihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9561818
    Abstract: A suspension apparatus for steered wheel includes a knuckle as a supporting member for rotatably supporting the steered wheel, two lower arms separately connected to joints as two lower-part connecting points equipped on lower part of the knuckle respectively, and two upper arms separately connected to joints as two upper-part connecting points equipped on an upper part of the knuckle respectively, and, connecting points of the two lower arms and the two upper arms to the knuckle are configured such that a rate of moving amount toward the vehicle inside to moving amount toward the vehicle front of a second extended line AP2 connecting the two joints straightly is more than the rate of a first extended line AP1 connecting the two joints straightly.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: February 7, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Takeshi Uchihara
  • Patent number: 9412825
    Abstract: A semiconductor device includes a GaN-based semiconductor layer, a source electrode on the GaN-based semiconductor layer, a drain electrode on the GaN-based semiconductor layer, and a gate electrode formed on the GaN-based semiconductor layer between the source electrode and the drain electrode. A first layer is in contact with the GaN-based semiconductor layer between the gate electrode and the drain electrode.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: August 9, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takaaki Yasumoto, Naoko Yanase, Kazuhide Abe, Takeshi Uchihara, Yasunobu Saito, Toshiyuki Naka, Akira Yoshioka, Tasuku Ono, Tetsuya Ohno, Hidetoshi Fujimoto, Shingo Masuko, Masaru Furukawa, Yasunari Yagi, Miki Yumoto, Atsuko Iida, Yukako Murakami, Takako Motai
  • Publication number: 20160083004
    Abstract: A suspension apparatus for steered wheel includes a knuckle as a supporting member for rotatably supporting the steered wheel, two lower arms separately connected to joints as two lower-part connecting points equipped on lower part of the knuckle respectively, and two upper arms separately connected to joints as two upper-part connecting points equipped on an upper part of the knuckle respectively, and, connecting points of the two lower arms and the two upper arms to the knuckle are configured such that a rate of moving amount toward the vehicle inside to moving amount toward the vehicle front of a second extended line AP2 connecting the two joints straightly is more than the rate of a first extended line AP1 connecting the two joints straightly.
    Type: Application
    Filed: February 13, 2014
    Publication date: March 24, 2016
    Inventor: Takeshi UCHIHARA
  • Publication number: 20160079373
    Abstract: A semiconductor device includes a compound semiconductor layer, an insulating element, and a conductive element. The conductive element includes a plurality of conductive regions which are spaced from the compound semiconductor layer in a first direction. The insulating element is provided between the compound semiconductor layer and the conductive element. A length of each of the plurality of conductive regions in a second direction which intersects the first direction becomes longer the farther the individual one of the plurality of conductive regions is spaced from the compound semiconductor layer.
    Type: Application
    Filed: March 2, 2015
    Publication date: March 17, 2016
    Inventors: Takeshi UCHIHARA, Wataru SAITO, Takaaki YASUMOTO, Naoko YANASE
  • Publication number: 20160079410
    Abstract: A semiconductor device includes a first electrode, a second electrode, a third electrode, and a nitride semiconductor layer. The first electrode has a first surface. The second electrode has a second surface. The second surface is provided with a plurality of convex portions and concave portions. The second electrode is spaced from the first electrode in a first direction. The third electrode is spaced from the first electrode in a second direction intersecting the first direction. The nitride semiconductor layer is provided between the first surface and the second surface, and between the third electrode and the second surface.
    Type: Application
    Filed: March 3, 2015
    Publication date: March 17, 2016
    Inventors: Takaaki YASUMOTO, Naoko YANASE, Kazuhide ABE, Takeshi UCHIHARA, Yasunobu SAITO, Hidetoshi FUJIMOTO, Masaru FURUKAWA, Yasunari YAGI, Miki YUMOTO, Atsuko IIDA, Yukako MURAKAMI
  • Patent number: 9254519
    Abstract: Provided is a composite material suitable for forming a part for continuous casting capable of producing cast materials of excellent surface quality for a long period of time and with which a molten metal is inhibited from flowing into a gap between a nozzle and a moving mold. A composite material (nozzle 1) includes a porous body 2 having a large number of pores and a filler incorporated in at least part of a portion that comes into contact with the molten metal, the portion being part of a surface portion of the porous body. The filler incorporated in the porous body 2 is at least one selected from a nitride, a carbide, and carbon.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: February 9, 2016
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Michimasa Miyanaga, Takeshi Uchihara, Masatada Numano, Yukihiro Oishi, Nozomu Kawabe
  • Patent number: 9222160
    Abstract: A coil material capable of contributing to an improvement of the productivity of a high-strength magnesium alloy sheet and a method for manufacturing the coil material are provided. Regarding the method for manufacturing a coil material through coiling of a sheet material formed from a metal into the shape of a cylinder, so as to produce the coil material, the sheet material is a cast material of a magnesium alloy discharged from a continuous casting machine and the thickness t (mm) thereof is 7 mm or less. The sheet material 1 is coiled with a coiler while the temperature T (° C.) of the sheet material 1 just before coiling is controlled to be a temperature at which the surface strain ((t/R)×100) represented by the thickness t and the bending radius R (mm) of the sheet material 1 becomes less than or equal to the elongation at room temperature of the sheet material 1.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: December 29, 2015
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Masatada Numano, Michimasa Miyanaga, Takeshi Uchihara, Yukihiro Oishi, Nozomu Kawabe
  • Patent number: 9165922
    Abstract: According to an embodiment, a semiconductor device includes a conductive substrate, a Schottky barrier diode, and a field-effect transistor. The Schottky barrier diode is mounted on the conductive substrate and includes an anode electrode and a cathode electrode. The anode electrode is electrically connected to the conductive substrate. The field-effect transistor is mounted on the conductive substrate and includes a source electrode, a drain electrode, and a gate electrode. The source electrode of the field-effect transistor is electrically connected to the cathode electrode of the Schottky barrier diode. The gate electrode of the field-effect transistor is electrically connected to the anode electrode of the Schottky barrier diode.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: October 20, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Yoshioka, Yasunobu Saito, Hidetoshi Fujimoto, Takeshi Uchihara, Naoko Yanase, Toshiyuki Naka, Tetsuya Ohno, Tasuku Ono
  • Publication number: 20150263103
    Abstract: A semiconductor device according to an embodiment includes a first semiconductor layer including a first nitride semiconductor, a second semiconductor layer on the first semiconductor layer including a second nitride semiconductor, a source electrode, a drain electrode, a first gate electrode provided on the second semiconductor layer between the source electrode and the drain electrode having a schottky junction, a second gate electrode provided above the second semiconductor layer intervening an insulating film, provided between the source electrode and the first gate electrode, electrically connected with the first gate electrode, and a third gate electrode provided above the second semiconductor layer intervening an insulating film, provided between the drain electrode and the first gate electrode, electrically connected with the first gate electrode.
    Type: Application
    Filed: March 17, 2014
    Publication date: September 17, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yasunobu Saito, Hidetoshi Fujimoto, Akira Yoshioka, Takeshi Uchihara, Takaaki Yasumoto, Naoko Yanase, Tasuku Ono
  • Publication number: 20150263152
    Abstract: A semiconductor device includes a GaN-based semiconductor layer, a source electrode on the GaN-based semiconductor layer, a drain electrode on the GaN-based semiconductor layer, and a gate electrode formed on the GaN-based semiconductor layer between the source electrode and the drain electrode. A first layer is in contact with the GaN-based semiconductor layer between the gate electrode and the drain electrode.
    Type: Application
    Filed: August 29, 2014
    Publication date: September 17, 2015
    Inventors: Takaaki YASUMOTO, Naoko YANASE, Kazuhide ABE, Takeshi UCHIHARA, Yasunobu SAITO, Toshiyuki NAKA, Akira YOSHIOKA, Tasuku ONO, Tetsuya OHNO, Hidetoshi FUJIMOTO, Shingo MASUKO, Masaru FURUKAWA, Yasunari YAGI, Miki YUMOTO, Atsuko IIDA, Yukako MURAKAMI, Takako MOTAI
  • Publication number: 20150263101
    Abstract: In one embodiment, a semiconductor device includes a semiconductor chip including a nitride semiconductor layer, and including a control electrode, a first electrode and a second electrode provided on the nitride semiconductor layer. The device further includes a support including a substrate, and including a control terminal, a first terminal and a second terminal provided on the substrate. The semiconductor chip is provided on the support such that the control electrode, the first electrode and the second electrode face the support. The control electrode, the first electrode and the second electrode of the semiconductor chip are electrically connected to the control terminal, the first terminal and the second terminal of the support, respectively.
    Type: Application
    Filed: September 10, 2014
    Publication date: September 17, 2015
    Inventors: Shingo Masuko, Takaaki Yasumoto, Naoko Yanase, Miki Yumoto, Masahito Mimura, Yasunobu Saito, Akira Yoshioka, Hidetoshi Fujimoto, Takeshi Uchihara, Tetsuya Ohno, Toshiyuki Naka, Tasuku Ono
  • Publication number: 20150263001
    Abstract: A semiconductor device includes a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. A first control electrode is on the first semiconductor layer with a first insulating layer between the first control electrode and the first semiconductor layer. A second control electrode is on the first semiconductor layer with a second insulating layer between the second control electrode and the first semiconductor layer, a distance between the first control electrode and the first semiconductor layer is less than a distance between the second control electrode. A wiring electrically connects the first control electrode and the second control electrode.
    Type: Application
    Filed: August 29, 2014
    Publication date: September 17, 2015
    Inventors: Yasunobu SAITO, Hidetoshi FUJIMOTO, Akira YOSHIOKA, Takeshi UCHIHARA, Toshiyuki NAKA, Tasuku ONO
  • Publication number: 20150263630
    Abstract: In one embodiment, a power supply circuit includes a first circuit including one or more first switching devices, and a first controller configured to control the first switching devices, the first circuit being configured to output a first voltage. The power supply circuit further includes a second circuit including one or more second switching devices which include a normally-on device, and a second controller configured to control the second switching devices, the second circuit being configured to output a second voltage generated from the first voltage. The second controller transmits a first signal for allowing the first circuit to output the first voltage, based on a value of a voltage or a current at a first node in the second circuit. The first controller allows the first circuit to output the first voltage by controlling the first switching devices in accordance with the first signal.
    Type: Application
    Filed: September 10, 2014
    Publication date: September 17, 2015
    Inventors: Toshiyuki Naka, Yasunobu Saito, Hidetoshi Fujimoto, Akira Yoshioka, Tetsuya Ohno, Takeshi Uchihara, Takaaki Yasumoto, Naoko Yanase, Shingo Masuko, Tasuku Ono
  • Publication number: 20150263700
    Abstract: According to one embodiment, a semiconductor device includes a GaN-based semiconductor layer, a resonator that uses a first portion of the GaN-based semiconductor layer as a piezoelectric layer to resonate, and a transistor that uses a second portion of the GaN-based semiconductor layer as a channel layer.
    Type: Application
    Filed: September 2, 2014
    Publication date: September 17, 2015
    Inventors: Takaaki YASUMOTO, Naoko YANASE, Kazuhide ABE, Takeshi UCHIHARA, Yasunobu SAITO, Toshiyuki NAKA, Akira YOSHIOKA, Tasuku ONO, Tetsuya OHNO, Hidetoshi FUJIMOTO, Shingo MASUKO, Masaru FURUKAWA, Yasunari YAGI, Miki YUMOTO, Atsuko IIDA, Yukako MURAKAMI, Yoshikazu SUZUKI
  • Patent number: 9054171
    Abstract: In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type or an intrinsic type. The device further includes a second semiconductor layer of the first conductivity type or the intrinsic type disposed above the first semiconductor layer. The device further includes a third semiconductor layer of a second conductivity type including a first upper portion in contact with the first semiconductor layer, a second upper portion located at a lower position than the first upper portion, a first side portion located between the first upper portion and the second upper portion, and a second side portion located at a lower position than the first side portion.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: June 9, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Ohno, Yasunobu Saito, Hidetoshi Fujimoto, Akira Yoshioka, Takeshi Uchihara, Toshiyuki Naka, Takaaki Yasumoto, Naoko Yanase, Shingo Masuko, Tasuku Ono
  • Publication number: 20150076506
    Abstract: This disclosure provides a semiconductor device which includes a GaN-based semiconductor layer having a surface with an angle of not less than 0 degree and not more than 5 degrees with respect to an m-plane or an a-plane, a first electrode provided above the surface and having a first end, and a second electrode provided above the surface to space apart from the first electrode, having a second end facing the first end, and a direction of a segment connecting an arbitrary point of the first end and an arbitrary point of the second end is different from a c-axis direction of the GaN-based semiconductor layer.
    Type: Application
    Filed: March 17, 2014
    Publication date: March 19, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takaaki Yasumoto, Naoko Yanase, Kazuhide Abe, Takeshi Uchihara, Yasunobu Saito, Toshiyuki Naka, Akira Yoshioka, Tasuku Ono, Tetsuya Ohno, Hidetoshi Fujimoto, Shingo Masuko, Masaru Furukawa, Yasunari Yagi, Miki Yumoto, Atsuko Iida
  • Publication number: 20150069468
    Abstract: In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type or an intrinsic type. The device further includes a second semiconductor layer of the first conductivity type or the intrinsic type disposed above the first semiconductor layer. The device further includes a third semiconductor layer of a second conductivity type including a first upper portion in contact with the first semiconductor layer, a second upper portion located at a lower position than the first upper portion, a first side portion located between the first upper portion and the second upper portion, and a second side portion located at a lower position than the first side portion.
    Type: Application
    Filed: March 7, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsuya Ohno, Yasunobu Saito, Hidetoshi Fujimoto, Akira Yoshioka, Takeshi Uchihara, Toshiyuki Naka, Takaaki Yasumoto, Naoko Yanase, Shingo Masuko, Tasuku Ono
  • Publication number: 20140284610
    Abstract: According to an embodiment, a semiconductor device includes a conductive substrate, a Schottky barrier diode, and a field-effect transistor. The Schottky barrier diode is mounted on the conductive substrate and includes an anode electrode and a cathode electrode. The anode electrode is electrically connected to the conductive substrate. The field-effect transistor is mounted on the conductive substrate and includes a source electrode, a drain electrode, and a gate electrode. The source electrode of the field-effect transistor is electrically connected to the cathode electrode of the Schottky barrier diode. The gate electrode of the field-effect transistor is electrically connected to the anode electrode of the Schottky barrier diode.
    Type: Application
    Filed: August 30, 2013
    Publication date: September 25, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira YOSHIOKA, Yasunobu SAITO, Hidetoshi FUJIMOTO, Takeshi UCHIHARA, Naoko YANASE, Toshiyuki NAKA, Tetsuya OHNO, Tasuku ONO
  • Publication number: 20130248998
    Abstract: According to one embodiment, a semiconductor device includes, a drain, source, base and drift regions, a gate electrode, a gate insulating film, a first semiconductor region, a drain electrode, and a source electrode. The drain region has a first portion, and a second portion having a surface extending in a first direction which is vertical to a main surface of the first portion. The source region extends in a second direction which is parallel to the second portion, and is provided to be spaced from the drain region. The gate electrode extends in the first direction and a third direction which is vertical to the first direction and the second direction, and passes through the base region in the third direction. The first semiconductor region is provided between the gate insulating film and the drain region, and has a lower impurity concentration than the drift region.
    Type: Application
    Filed: September 14, 2012
    Publication date: September 26, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shinichiro Misu, Tsuyoshi Ota, Tatsuya Nishiwaki, Takeshi Uchihara, Yusuke Kawaguchi
  • Patent number: 8482060
    Abstract: According to one embodiment, a semiconductor device includes a drift region of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity type, a gate electrode in a trench shape, a contact region of the second conductivity type, a drain electrode, and a source electrode. The drift region is selectively provided in a drain layer of the first conductivity type from a surface of the drain layer to an inside of the drain layer. The base region is selectively provided in the drift region from a surface of the drift region to an inside of the drift region. The source region is selectively provided in the base region from a surface of the base region to an inside of the base region. The gate electrode penetrates from a part of the source region through the base region adjacent to the part of the source region to reach a part of the drift region in a direction substantially parallel to a major surface of the drain layer.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: July 9, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Uchihara, Yusuke Kawaguchi, Keiko Kawamura, Hitoshi Shinohara, Yosefu Fujiki