Patents by Inventor Takeshi Uenoyama

Takeshi Uenoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020027236
    Abstract: An n-GaN layer is provided as an emitter layer for supplying electrons. A non-doped (intrinsic) AlxGa1−xN layer (0≦x≦1) having a compositionally graded Al content ratio x is provided as an electron transfer layer for transferring electrons toward the surface. A non-doped AlN layer having a negative electron affinity (NEA) is provided as a surface layer. Above the AlN layer, a control electrode and a collecting electrode are provided. An insulating layer formed of a material having a larger electron affinity than that of the AlN layer is interposed between the control electrode and the collecting electrode. This provides a junction transistor which allows electrons injected from the AlN layer to conduct through the conduction band of the insulating layer and then reach the collecting electrode.
    Type: Application
    Filed: August 8, 2001
    Publication date: March 7, 2002
    Inventors: Takeshi Uenoyama, Masahiro Deguchi
  • Patent number: 6350999
    Abstract: In an electron-emitting device, an electron supplying layer for supplying electrons is composed of an n-GaN layer. An electron transferring layer for moving electrons toward the surface is composed of non-doped (intrinsic) AlxGa1−xN (0≦x≦1) having a graded composition for the Al concentration x. A surface layer is composed of non-doped AlN having a negative electron affinity (NEA). The electron transferring layer composed of AlxGa1−xN has a band gap which is enlarged nearly continuously from the electron supplying layer to the surface layer and a negative electron affinity or a positive electron affinity close to zero. If such a voltage V as to render the surface electrode side positive is applied, the band of AlxGa1−xN is bent, whereby a current derived mainly from a diffused current flows from the electron supplying layer to the surface layer through the electron transferring layer. Thereby excellent electron emitting characteristic is obtained.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: February 26, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Uenoyama, Takao Tohda, Masahiro Deguchi, Makoto Kitabatake, Kentaro Setsune
  • Publication number: 20020011617
    Abstract: Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in this carrier accumulation layer serving as a channel. In the SiGeC layer, the electron mobility is greater than in silicon, thus increasing the NMOS transistor in operational speed. In a PMOS transistor, a channel in which positive holes travel, is formed with the use of a discontinuous portion of a valence band at the interface between the SiGe and Si layers. In the SiGe layer, too, the positive hole mobility is greater than in the Si layer, thus increasing the PMOS transistor in operational speed. There can be provided a semiconductor device having field-effect transistors having channels lessened in crystal defect.
    Type: Application
    Filed: September 16, 1997
    Publication date: January 31, 2002
    Inventors: MINORU KUBO, KATSUYA NOZAWA, MASAKATSU SUZUKI, TAKESHI UENOYAMA, YASUHITO KUMABUCHI
  • Publication number: 20010053561
    Abstract: An insulated-gate semiconductor element with a trench structure is provided, which has a high breakdown voltage even though a silicon carbide substrate is used that is preferable to obtain a semiconductor element with favorable properties. The surface of a silicon carbide substrate is etched to form a concave portion. Then, a particle beam, for example an ion beam, is irradiated from above, and a defect layer is formed at least in a bottom surface of the concave portion. The substrate is heated in an oxidation atmosphere, and an oxide film is formed at least on a side surface and the bottom surface of the concave portion. Then, a gate electrode is formed on the oxide film.
    Type: Application
    Filed: March 1, 2001
    Publication date: December 20, 2001
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Makoto Kitabatake, Masao Uchida, Kunimasa Takahashi, Takeshi Uenoyama
  • Patent number: 6326638
    Abstract: The semiconductor laser of this invention includes an active layer formed in a c-axis direction, wherein the active layer is made of a hexagonal-system compound semiconductor, and anisotropic strain is generated in a c plane of the active layer.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: December 4, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Satoshi Kamiyama, Masakatsu Suzuki, Takeshi Uenoyama, Kiyoshi Ohnaka, Akira Takamori, Masaya Mannoh, Isao Kidoguchi, Hideto Adachi, Akihiko Ishibashi, Toshiya Fukuhisa, Yasuhito Kumabuchi
  • Patent number: 6228720
    Abstract: An insulated-gate semiconductor element with a trench structure is provided, which has a high breakdown voltage even though a silicon carbide substrate is used that is preferable to obtain a semiconductor element with favorable properties. The surface of a silicon carbide substrate is etched to form a concave portion. Then, a particle beam, for example an ion beam, is irradiated from above, and a defect layer is formed at least in a bottom surface of the concave portion. The substrate is heated in an oxidation atmosphere, and an oxide film is formed at least on a side surface and the bottom surface of the concave portion. Then, a gate electrode is formed on the oxide film.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: May 8, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Makoto Kitabatake, Masao Uchida, Kunimasa Takahashi, Takeshi Uenoyama
  • Patent number: 6190975
    Abstract: Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in this carrier accumulation layer serving as a channel. In the SiGeC layer, the electron mobility is greater than in silicon, thus increasing the NMOS transistor in operational speed. In a PMOS transistor, a channel in which positive holes travel, is formed with the use of a discontinuous portion of a valence band at the interface between the SiGe and Si layers. In the SiGe layer, too, the positive hole mobility is greater than in the Si layer, thus increasing the PMOS transistor in operational speed. There can be provided a semiconductor device having field-effect transistors having channels lessened in crystal defect.
    Type: Grant
    Filed: December 9, 1998
    Date of Patent: February 20, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Minoru Kubo, Katsuya Nozawa, Masakatsu Suzuki, Takeshi Uenoyama, Yasuhito Kumabuchi
  • Patent number: 6141364
    Abstract: A semiconductor laser device of the present invention includes a substrate 201 made of n-type GaAs, an active layer 204, and a pair of cladding layers sandwiching the active layer 204. The device further includes a spacer layer 205 adjacent to the active layer 204 and a highly doped saturable absorbing layer 206. The carrier life time is shortened by doping the saturable absorbing layer 206 in a high concentration, whereby stable self-sustained pulsation can be obtained. As a result, a semiconductor laser device can be obtained, which has a low relative noise intensity in a wide range of temperatures.
    Type: Grant
    Filed: July 8, 1999
    Date of Patent: October 31, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd
    Inventors: Hideto Adachi, Satoshi Kamiyama, Isao Kidoguchi, Takeshi Uenoyama, Masaya Mannoh, Toshiya Fukuhisa
  • Patent number: 6081541
    Abstract: A semiconductor laser device of the present invention includes a substrate 201 made of n-type GaAs, an active layer 204, and a pair of cladding layers sandwiching the active layer 204. The device further includes a spacer layer 205 adjacent to the active layer 204 and a highly doped saturable absorbing layer 206. The carrier life time is shortened by doping the saturable absorbing layer 206 in a high concentration, whereby stable self-sustained pulsation can be obtained. As a result, a semiconductor laser device can be obtained, which has a low relative noise intensity in a wide range of temperatures.
    Type: Grant
    Filed: July 8, 1999
    Date of Patent: June 27, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideto Adachi, Satoshi Kamiyama, Isao Kidoguchi, Takeshi Uenoyama, Masaya Mannoh, Toshiya Fukuhisa
  • Patent number: 6072817
    Abstract: A semiconductor laser device of the present invention includes a substrate 201 made of n-type GaAs, an active layer 204, and a pair of cladding layers sandwiching the active layer 204. The device further includes a spacer layer 205 adjacent to the active layer 204 and a highly doped saturable absorbing layer 206. The carrier life time is shortened by doping the saturable absorbing layer 206 in a high concentration, whereby stable self-sustained pulsation can be obtained. As a result, a semiconductor laser device can be obtained, which has a low relative noise intensity in a wide range of temperatures.
    Type: Grant
    Filed: October 30, 1996
    Date of Patent: June 6, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideto Adachi, Satoshi Kamiyama, Isao Kidoguchi, Takeshi Uenoyama, Masaya Mannoh, Toshiya Fukuhisa
  • Patent number: 6055253
    Abstract: A semiconductor laser device having an active layer, a pair of cladding layers interposing the active layer and a multi-quantum barrier provided between one of the pair of cladding layers and the active layer is provided, and the multi-quantum barrier includes barrier layers and well layers being alternated with each other. The semiconductor laser device also including an optical guide layer confining light generated in a quantum well layer, and the optical guide layer being undoped.
    Type: Grant
    Filed: March 1, 1995
    Date of Patent: April 25, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Isao Kidoguchi, Kiyoshi Ohnaka, Hideto Adachi, Satoshi Kamiyama, Masaya Mannou, Takeshi Uenoyama
  • Patent number: 5787104
    Abstract: The semiconductor laser of this invention includes an active layer formed in a c-axis direction, wherein the active layer is made of a hexagonal-system compound semiconductor, and anisotropic strain is generated in a c plane of the active layer.
    Type: Grant
    Filed: January 19, 1996
    Date of Patent: July 28, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Satoshi Kamiyama, Masakatsu Suzuki, Takeshi Uenoyama, Kiyoshi Ohnaka, Akira Takamori, Masaya Mannoh, Isao Kidoguchi, Hideto Adachi, Akihiko Ishibashi, Toshiya Fukuhisa, Yasuhito Kumabuchi
  • Patent number: 5705831
    Abstract: According to one aspect of the invention, a crystal-growing method for forming a II-VI single crystalline semiconductor expressed by Zn.sub.1-x Cd.sub.x Se (where 0<x<0.35) is provided. The crystal-growing method includes a step of epitaxially growing the II-VI single crystalline semiconductor on a substrate by: supplying a II element Zn onto the substrate by using a molecular beam from a ZnSe compound source and a molecular beam from a Zn elemental source; supplying a II element Cd onto the substrate by using a molecular beam from a CdSe compound source; and supplying a VI element Se onto the substrate by using a molecular beam from a ZnSe compound source.
    Type: Grant
    Filed: April 3, 1995
    Date of Patent: January 6, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Nobuyuki Uemura, Minoru Kubo, Yoichi Sasai, Kazuhiro Ohkawa, Satoshi Kamiyama, Takeshi Uenoyama
  • Patent number: 5691936
    Abstract: A magnetoresistive effect element having a large magnetoresistive change with a small magnetic field, and a memory element using the same. A semiconductor film to provide a window for excitation light is arranged on a substrate via a buffer layer. Another semiconductor film and a nonmagnetic metallic film (or a nonmagnetic insulating film) are arranged on the semiconductor film successively. A magnetic film having a square magnetization curve is arranged on the nonmagnetic metallic film (or a nonmagnetic insulating film). An electrode is arranged beneath the substrate and another electrode is arranged on the magnetic film. By radiating a laser light beam to the semiconductor film acting as a window, electrons having spin polarization are excited in the semiconductor film so as to utilize the dependency of the scattering of electrons at the surface of the magnetic film on the magnetization orientation of the magnetic film and the spin polarization state of the excited electrons.
    Type: Grant
    Filed: August 14, 1996
    Date of Patent: November 25, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroshi Sakakima, Takeshi Uenoyama, Yasuhiro Kawawake, Yousuke Irie
  • Patent number: 5665978
    Abstract: An n-type diffusion layer, an insulating layer and a first aluminum electrode are formed on a p-type silicon substrate. Fe.sup.2+ (divalent Fe) having a vacant orbit not filled with an electron is implanted into a region of the insulating layer to form an impurity atom layer. A second aluminum electrode is formed which is in contact with the n-type diffusion layer. A voltage that increases the potential of the first aluminum electrode is applied between the first and second aluminum electrodes. The voltage is increased. In this situation, when the fermi level of the n-type diffusion layer and an impurity level which is the energy level for filling the vacant orbit of the Fe.sup.2+ are matched, a resonance tunnelling current flows. Thereafter, when there is a change to the state of non-resonance state, a negative-resistance characteristic is exhibited in which the current decreases as the voltage is increased.
    Type: Grant
    Filed: May 24, 1996
    Date of Patent: September 9, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Uenoyama, Yasuhito Kumabuchi
  • Patent number: 5600667
    Abstract: A semiconductor laser device having an active layer, a pair of cladding layers interposing the active layer and a multi-quantum barrier provided between one of the pair of cladding layers and the active layer is provided. The multi-quantum barrier includes barrier layers and well layers being alternated with each other. Thickness, energy band gap, or impurity concentration of at least one of the barrier layers and well layers in the multi-quantum barrier changes with the distance from the active layer, thereby providing a stable function of reflecting carriers overflowing from the active layer back to the active layer.
    Type: Grant
    Filed: April 5, 1994
    Date of Patent: February 4, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Isao Kidoguchi, Kiyoshi Ohnaka, Hideto Adachi, Satoshi Kamiyama, Masaya Mannou, Takeshi Uenoyama
  • Patent number: 5502739
    Abstract: A semiconductor laser device having an active layer, a pair of cladding layers interposing the active layer and a multi-quantum barrier provided between one of the pair of cladding layers and the active layer is provided. The multi-quantum barrier includes barrier layers and well layers being alternated with each other. Thickness, energy band gap, or impurity concentration of at least one of the barrier layers and well layers in the multi-quantum barrier changes with the distance from the active layer, thereby providing a stable function of reflecting carriers overflowing from the active layer back to the active layer.
    Type: Grant
    Filed: March 1, 1995
    Date of Patent: March 26, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Isao Kidoguchi, Kiyoshi Ohnaka, Hideto Adachi, Satoshi Kamiyama, Masaya Mannou, Takeshi Uenoyama