Patents by Inventor Takeshi Yamakawa

Takeshi Yamakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5017817
    Abstract: Disclosed are basic circuits operable in a current mode in multivalued logic circuit systems, analog circuit systems and the like. Examples of the basic circuits are a successor, quantizer, adder, subtractor, divider, multiplier, decoder, literal circuit, equivalence circuit, bilateral T-gate, complement literal circuit and h operator circuit. These basic circuits are realized by using floating threshold switching circuits, floating window switching circuits, threshold SPDT switching circuits, and the like.
    Type: Grant
    Filed: January 13, 1989
    Date of Patent: May 21, 1991
    Assignee: Omron Tateisi Electronics Co.
    Inventor: Takeshi Yamakawa
  • Patent number: 4996561
    Abstract: An image forming apparatus operable with an editor which can be mounted on a body of the apparatus together with a document handler and has space for accommodating an editor is defined within the apparatus between optics including a scanner and a photoconductive element located below the optics. The editor is movable into and out of the space through an opening which is formed through the apparatus, as desired.
    Type: Grant
    Filed: October 3, 1989
    Date of Patent: February 26, 1991
    Assignee: Ricoh Company, Ltd.
    Inventors: Tsuyoshi Yoshimura, Takeshi Yamakawa
  • Patent number: 4914614
    Abstract: A multivalued ALU is composed of a multivalued signal source, a memory array, a selection array, an AND array and an output circuit. The multivalued signal source generates signals each of which represents a logic value of multivalued logic. The memory array is provided with an address line group for each and every function to be implemented, each address line group comprising a number of address lines. Which multivalued logic signals will appear on the address lines of each address line group depends upon a program based on the truth table of the corresponding function. Any one of the plural address line groups is selected by the selection array, to which a signal designating the function to be implemented is applied. One address line in the selected address line group is selected by the AND array, which has an input signal applied thereto, and the logic value signal on the selected line is delivered via the output circuit.
    Type: Grant
    Filed: March 2, 1987
    Date of Patent: April 3, 1990
    Assignee: Omron Tateisi Electronics Co.
    Inventor: Takeshi Yamakawa
  • Patent number: 4875184
    Abstract: A fuzzy computer basically includes a plurality of fuzzy membership function generator circuits, and a fuzzy inference engine for executing a predetermined fuzzy operation among fuzzy membership functions that have been generated. A fuzzy membership function is represented by electric signals distributed on a plurality of lines.
    Type: Grant
    Filed: November 5, 1987
    Date of Patent: October 17, 1989
    Assignee: Omron Tateisi Electronics Co.
    Inventor: Takeshi Yamakawa
  • Patent number: 4860243
    Abstract: A fuzzy logic circuit comprising a current mirror comprising an FET, a first input current source connected to the input side of the current mirror, a second input current source, a wired OR connected at its input side to the output side of the current mirror and to the second input current source, and an output terminal connected to the output side of the wired OR.
    Type: Grant
    Filed: April 23, 1987
    Date of Patent: August 22, 1989
    Assignee: Omron Tateisi Electronics Co.
    Inventors: Fumio Ueno, Takeshi Yamakawa, Yuji Shirai
  • Patent number: 4837725
    Abstract: A programmable multi-membership function circuit comprises at least one or preferably two Z function circuits, at least one or preferably two S function circuits, and a fuzzy logic circuit for calculating fuzzy logic from the output of the Z function circuits and the output of the S function circuits. The fuzzy logic circuit comprises a MIN (intersection) circuit and a MAX (union) circuit, or the combination of these circuits.
    Type: Grant
    Filed: October 14, 1986
    Date of Patent: June 6, 1989
    Assignee: Omron Tateisi Electronics Co.
    Inventor: Takeshi Yamakawa
  • Patent number: 4814644
    Abstract: Disclosed are basic circuits operable in a current mode in multivalued logic circuit systems, analog circuit systems and the like. Examples of the basic circuits are a successor, quantizer, adder, substracter, divider, multiplier, decoder, literal circuit, equivalence circuit, bilateral T-gate, complement literal circuit and h operator circuit. These basic circuits are realized by using floating threshold switching circuits, floating window switching circuits, threshold SPDT switching circuits, and the like.
    Type: Grant
    Filed: January 22, 1986
    Date of Patent: March 21, 1989
    Assignee: K. Ushiku & Co.
    Inventor: Takeshi Yamakawa
  • Patent number: 4716540
    Abstract: A multi-functional fuzzy logic circuit comprises at least one input circuit provided for at least one input current for producing at least one output current of the same value in the same direction as the input current and at least one output current of the same value in the reverse direction, and a plurality of fuzzy logic circuits for executing different fuzzy logic operations, each of the fuzzy logic circuits having as its input at least one of said output currents produced by said input circuit.
    Type: Grant
    Filed: July 3, 1985
    Date of Patent: December 29, 1987
    Assignee: Omron Tateisi Electronics Co.
    Inventor: Takeshi Yamakawa
  • Patent number: 4694418
    Abstract: A fuzzy logic circuit comprising a current mirror comprising an FET, a first input current source connected to the input side of the current mirror, a second input current source, a wired OR connected at its input side to the output side of the current mirror and to the second input current source, and an output terminal connected to the output side of the wired OR.
    Type: Grant
    Filed: March 22, 1985
    Date of Patent: September 15, 1987
    Assignee: Omron Tateisi Electronics Co.
    Inventors: Fumio Ueno, Takeshi Yamakawa, Yuji Shirai