Patents by Inventor Takeshi Yanata

Takeshi Yanata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210327616
    Abstract: A chip varistor includes an element body exhibiting varistor characteristics, internal electrodes containing a first electrically conductive material, and an intermediate conductor containing a second electrically conductive material. The intermediate conductor is separated from the internal electrodes in a direction in which the internal electrodes oppose each other, and is disposed between the internal electrodes. At least a part of the intermediate conductor overlaps the internal electrodes in the direction in which the internal electrodes oppose each other. The element body includes a low resistance region in which the second electrically conductive material is diffused. The low resistance region is located between the first and second internal electrodes in the direction in which the first and second internal electrodes oppose each other.
    Type: Application
    Filed: April 14, 2021
    Publication date: October 21, 2021
    Applicant: TDK CORPORATION
    Inventors: Satoshi GOTO, Naoyoshi YOSHIDA, Takeshi YANATA, Takeshi OYANAGI, Daiki SUZUKI, Shin KAGAYA, Masayuki UCHIDA, Yusuke IMAI
  • Patent number: 9762203
    Abstract: A piezoelectric device has: a ceramic substrate having a first principal surface and a second principal surface opposed to each other; a piezoelectric element arranged on the first principal surface; a frame having a first face and a second face opposed to each other and arranged on the ceramic substrate so as to surround the piezoelectric element; a metal layer arranged on the second face of the frame; and a metal lid arranged on the metal layer so as to close a space surrounded by the frame. The first face of the frame is in contact with the first principal surface of the ceramic substrate. The metal layer and the metal lid are joined to each other by resistance welding. The frame has a composite portion containing a metal and a metal oxide and the composite portion includes the second face and is in contact with the metal layer.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: September 12, 2017
    Assignee: TDK CORPORATION
    Inventors: Takeshi Yanata, Yo Saito, Kazuto Takeya, Katsunari Moriai, Takashi Inagaki, Takahiro Itami, Takeshi Oyanagi, Hitoshi Ishida
  • Patent number: 9726552
    Abstract: Provided is a piezoelectric device capable of improving measurement precision of a temperature of a piezoelectric element. A piezoelectric device (1) includes a package (2) including a housing member (4) having a thermistor substrate (3) and a frame (7) provided to project from a first main surface (3a) of the thermistor substrate (3) and in which a housing part (6) is formed by the first main surface (3a) and the frame (7) and a lid (9) provided on the frame (7) to cover a space (5) of the housing part (6), and a piezoelectric vibration element (5) provided on the first main surface (3a) of the thermistor substrate (3) in the housing part (6), wherein the thermistor substrate (3) is a multilayer negative temperature coefficient (NTC) thermistor.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: August 8, 2017
    Assignee: TDK CORPORATION
    Inventors: Takeshi Yanata, Yo Saito, Kazuto Takeya, Katsunari Moriai, Takashi Inagaki, Takahiro Itami, Takeshi Oyanagi, Hitoshi Ishida
  • Publication number: 20150276504
    Abstract: Provided is a piezoelectric device capable of improving measurement precision of a temperature of a piezoelectric element. A piezoelectric device (1) includes a package (2) including a housing member (4) having a thermistor substrate (3) and a frame (7) provided to project from a first main surface (3a) of the thermistor substrate (3) and in which a housing part (6) is formed by the first main surface (3a) and the frame (7) and a lid (9) provided on the frame (7) to cover a space (5) of the housing part (6), and a piezoelectric vibration element (5) provided on the first main surface (3a) of the thermistor substrate (3) in the housing part (6), wherein the thermistor substrate (3) is a multilayer negative temperature coefficient (NTC) thermistor.
    Type: Application
    Filed: March 9, 2015
    Publication date: October 1, 2015
    Inventors: Takeshi YANATA, Yo SAITO, Kazuto TAKEYA, Katsunari MORIAI, Takashi INAGAKI, Takahiro ITAMI, Takeshi OYANAGI, Hitoshi ISHIDA
  • Publication number: 20150249199
    Abstract: A piezoelectric device has: a ceramic substrate having a first principal surface and a second principal surface opposed to each other; a piezoelectric element arranged on the first principal surface; a frame having a first face and a second face opposed to each other and arranged on the ceramic substrate so as to surround the piezoelectric element; a metal layer arranged on the second face of the frame; and a metal lid arranged on the metal layer so as to close a space surrounded by the frame. The first face of the frame is in contact with the first principal surface of the ceramic substrate. The metal layer and the metal lid are joined to each other by resistance welding. The frame has a composite portion containing a metal and a metal oxide and the composite portion includes the second face and is in contact with the metal layer.
    Type: Application
    Filed: January 14, 2015
    Publication date: September 3, 2015
    Inventors: Takeshi YANATA, Yo SAITO, Kazuto TAKEYA, Katsunari MORIAI, Takashi INAGAKI, Takahiro ITAMI, Takeshi OYANAGI, Hitoshi ISHIDA
  • Patent number: 7606018
    Abstract: A surge absorbing circuit has a substrate on which a first conductor, a second conductor, and a third conductor are placed, and a surge absorber having a first terminal and a second terminal. The first conductor and the second conductor are mutually coupled in a polarity-reversed relation. One end of the first conductor is connected to one end of the second conductor. The third conductor is electrically isolated from the first conductor and the second conductor on the substrate. The first terminal of the surge absorber is connected to a connection portion between the first conductor and the second conductor. The second terminal of the surge absorber is connected to the third conductor.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: October 20, 2009
    Assignee: TDK Corporation
    Inventors: Koichi Ishii, Yuji Terada, Takeshi Yanata
  • Patent number: 7446992
    Abstract: A connector which can reduce electrostatic surges without deteriorating high-speed signals is provided. The connector in accordance with the first embodiment of the present invention comprises a first terminal, a second terminal connected to the first terminal, and a surge absorbing circuit provided between the first and second terminals. The surge absorbing circuit comprises (a) a first inductor having one end connected to the first terminal; (b) a second inductor, electromagnetically coupled to the first inductor, having one end connected to the other end of the first inductor and the other end connected to the second terminal; and (c) a surge absorbing element having one end connected to the other end of the first inductor and the one end of the second inductor and the other end connected to a ground terminal.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: November 4, 2008
    Assignee: TDK Corporation
    Inventors: Yuji Terada, Koichi Ishii, Takeshi Yanata
  • Patent number: 7400485
    Abstract: A surge absorber has a first terminal electrode, a second terminal electrode, a third terminal electrode, an inductor portion, a surge absorbing portion, and a resistor portion. The inductor portion has a first internal conductor and a second internal conductor mutually coupled in a polarity-reversed relation. One end of the first internal conductor is connected to the first terminal electrode. One end of the second internal conductor is connected to the second terminal electrode. The other end of the first internal conductor is connected to the other end of the second internal conductor. The surge absorbing portion has a first internal electrode and a second internal electrode. The first internal electrode is connected to the other end of the first internal conductor and to the other end of the second internal conductor. The second internal electrode is connected to the third terminal electrode.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: July 15, 2008
    Assignee: TDK Corporation
    Inventors: Naoki Chida, Yuji Terada, Koichi Ishii, Takeshi Yanata, Dai Matsuoka
  • Publication number: 20070076343
    Abstract: A connector which can reduce electrostatic surges without deteriorating high-speed signals is provided. The connector in accordance with the first embodiment of the present invention comprises a first terminal, a second terminal connected to the first terminal, and a surge absorbing circuit provided between the first and second terminals. The surge absorbing circuit comprises (a) a first inductor having one end connected to the first terminal; (b) a second inductor, electromagnetically coupled to the first inductor, having one end connected to the other end of the first inductor and the other end connected to the second terminal; and (c) a surge absorbing element having one end connected to the other end of the first inductor and the one end of the second inductor and the other end connected to a ground terminal.
    Type: Application
    Filed: September 25, 2006
    Publication date: April 5, 2007
    Applicant: TDK CORPORATION
    Inventors: Yuji Terada, Koichi Ishii, Takeshi Yanata
  • Publication number: 20070070569
    Abstract: A surge absorber has a first terminal electrode, a second terminal electrode, a third terminal electrode, an inductor portion, a surge absorbing portion, and a resistor portion. The inductor portion has a first internal conductor and a second internal conductor mutually coupled in a polarity-reversed relation. One end of the first internal conductor is connected to the first terminal electrode. One end of the second internal conductor is connected to the second terminal electrode. The other end of the first internal conductor is connected to the other end of the second internal conductor. The surge absorbing portion has a first internal electrode and a second internal electrode. The first internal electrode is connected to the other end of the first internal conductor and to the other end of the second internal conductor. The second internal electrode is connected to the third terminal electrode.
    Type: Application
    Filed: August 11, 2006
    Publication date: March 29, 2007
    Applicant: TDK Corporation
    Inventors: Naoki Chida, Yuji Terada, Koichi Ishii, Takeshi Yanata, Dai Matsuoka
  • Publication number: 20070019353
    Abstract: A surge absorbing circuit has a substrate on which a first conductor, a second conductor, and a third conductor are placed, and a surge absorber having a first terminal and a second terminal. The first conductor and the second conductor are mutually coupled in a polarity-reversed relation. One end of the first conductor is connected to one end of the second conductor. The third conductor is electrically isolated from the first conductor and the second conductor on the substrate. The first terminal of the surge absorber is connected to a connection portion between the first conductor and the second conductor. The second terminal of the surge absorber is connected to the third conductor.
    Type: Application
    Filed: July 19, 2006
    Publication date: January 25, 2007
    Applicant: TDK Corporation
    Inventors: Koichi Ishii, Yuji Terada, Takeshi Yanata