Patents by Inventor Takeshi Yasuie

Takeshi Yasuie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160203056
    Abstract: An apparatus includes: a first memory configured to store a plurality of snapshots of a database; a second memory configured to store correspondence information for each of processing requests to the database, the correspondence information including a time at which each of the processing requests is accepted by the database in association with a time period taken for processing each of the processing requests; and a processor configured to: identify a total time period to process processing requests received by the database from a first time at which a first snapshot is obtained to a second time at which a second snapshot is obtained, the first snapshot and the second snapshot being included in the plurality of snapshots; decide a snapshot to be deleted from the plurality of snapshots based on the identified total time period; and delete the decided snapshot from the first memory.
    Type: Application
    Filed: December 23, 2015
    Publication date: July 14, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Toshihiro Shimizu, Takeshi Yasuie, Atsuji Sekiguchi
  • Patent number: 9391852
    Abstract: A computer is disclosed that performs a verification process. The computer analyzes quality characteristics of communication for each of predetermined quality analysis subjects from actual capture data. The computer generates send data based on the actual capture data and an exchanging message which is acquired when a reproduced operation is verified based on the actual capture data. The computer sends the send data to a verification subject apparatus at sending timing based on the quality characteristics. The computer receives response data from the verification subject apparatus. The computer verifies an operation of the verification subject apparatus.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: July 12, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Takeshi Yasuie, Taichi Sugiyama, Yuji Nomura
  • Publication number: 20160117224
    Abstract: An analysis method including: storing information on modules through which each processing passes with respect to each of a plurality of processings in which shared modules exist; determining a normal or abnormal state of each of the processings which are performed during a predetermined time interval based on log information related to the plurality of processings which are performed during the predetermined time interval; correcting the information on the modules according to each of the processings which are performed during the predetermined time interval, based on a predetermined condition, when an abnormal module is not identified in a process of identifying the abnormal module by using a determination result of the normal or abnormal state and the information on the modules according to each of the processings; and identifying the abnormal module by using the determination result and the corrected information on the modules.
    Type: Application
    Filed: August 21, 2015
    Publication date: April 28, 2016
    Inventors: Yuuji HOTTA, Takeshi Yasuie, Atsuji SEKIGUCHI, Toshihiro SHIMIZU
  • Publication number: 20160004710
    Abstract: A memory unit of an information processing apparatus acquires at least one operation log in work performed on a management target device and difference information indicating a difference between a file before edit and the file after edit that is edited using an editing software. A computing unit extracts a first log indicating an activation operation of the editing software used in editing the file, from the log. Then, the computing unit replaces the first log with a second log indicating an operation for reflecting in the file the difference indicated in the difference information.
    Type: Application
    Filed: June 17, 2015
    Publication date: January 7, 2016
    Inventors: Atsuji SEKIGUCHI, Toshihiro SHIMIZU, Takeshi Yasuie
  • Publication number: 20150331917
    Abstract: A computer obtains communication information that is transmitted/received between tiers in an information processing system providing a result of a process performed in an n-th (n>2) tier in reply to received request, identifies pairs of the request and corresponding response in each of the plurality of tiers from the obtained communication information, compares the pairs in each of tiers, extracts an order relationship wherein the request of a second pair is transmitted after the response of a first pair is obtained, obtains the order relationship in an (n-i)th tier on the basis of the order relationship between the pairs in an (n-i+1)th tier that respectively correspond to the pairs in the (n-i)th tier, sequentially from the n-th tier to a first tier, and determines a transmission order of the request to the information processing system on the basis of the obtained order relationship.
    Type: Application
    Filed: March 30, 2015
    Publication date: November 19, 2015
    Inventors: Toshihiro SHIMIZU, Takeshi Yasuie
  • Publication number: 20150254309
    Abstract: A determination unit determines a precondition indicating an expected state of a system that is to execute processing corresponding to an operation, and a postcondition indicating an expected state of the system that has executed the processing corresponding to the operation, based on a work log of previously-performed work. An association unit associates each of a plurality of operations with an operation whose precondition matches a postcondition of the each of the plurality of operations. A search unit searches for a path that starts from an operation whose precondition matches an initial condition satisfied by an operation object system, traces an associated operation, and reaches an operation whose postcondition matches a target condition indicating a target state of the operation object system after work. A generation unit generates an operation procedure in which operations on the path found by the search are arranged in order.
    Type: Application
    Filed: February 9, 2015
    Publication date: September 10, 2015
    Inventors: Atsuji SEKIGUCHI, Toshihiro SHIMIZU, Takeshi Yasuie
  • Publication number: 20150254293
    Abstract: An information processing method to be executed by a processor included in a verifying device configured to verify a program executed by a device, the information processing method includes storing order information indicating an order in which a plurality of packets are received by the verifying device; receiving packets transmitted by the device according to the program executed by the device; and controlling a timing to transmit a response to each of the received packets based on the order information.
    Type: Application
    Filed: February 9, 2015
    Publication date: September 10, 2015
    Inventors: Toshihiro SHIMIZU, Takeshi Yasuie
  • Publication number: 20150195214
    Abstract: A verification method includes storing a plurality of cache scenarios in which combinations of one or more data which are a caching object are defined, the caching object indicating an object to be stored in a first server whose processing speed is faster than that of a second server, the combinations being different from each other; acquiring a plurality of packets related to a request for data; estimating, by a processor, response time, which is response time to the request when using both the first server and the second server together for processing the plurality of packets, the response time corresponding to each of one or more cache scenarios among the plurality of cache scenarios, based on the plurality of acquired packets; and specifying a cache scenario which satisfies a predetermined threshold among the one or more cache scenarios based on the estimated response time.
    Type: Application
    Filed: December 17, 2014
    Publication date: July 9, 2015
    Inventors: Taichi Sugiyama, Takeshi Yasuie, Yuji NOMURA
  • Publication number: 20150135018
    Abstract: Common parameters in common between a plurality of request logs are extracted from parameters in the plurality of request logs. The plurality of request logs is obtained when a request is executed by a process that uses a plurality of components. A common parameter different from a common parameter extracted for another process among the extracted common parameters is determined as an identification parameter that identifies the process. This allows accurately categorizing the process based on a log to be obtained when the process is executed.
    Type: Application
    Filed: October 23, 2014
    Publication date: May 14, 2015
    Inventors: Yuuji HOTTA, Atsuji SEKIGUCHI, Takeshi Yasuie
  • Patent number: 9015830
    Abstract: A verification apparatus for verifying a verified apparatus corresponding to a first apparatus included in a plurality of information processing apparatuses includes a storage and a processor. The storage stores captured data acquired by capturing data transmitted and received among the plurality of information processing apparatuses. The processor receives first data transmitted from the verified apparatus. The first data is destined for a second apparatus included in the plurality of information processing apparatuses. The processor extracts, from the storage, second data transmitted from the second apparatus in response to third data transmitted from the first apparatus to the second apparatus. The third data corresponds to the first data. The processor transmits the extracted second data to the verified apparatus.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: April 21, 2015
    Assignee: Fujitsu Limited
    Inventors: Takeshi Yasuie, Yuji Nomura, Taichi Sugiyama
  • Patent number: 8996694
    Abstract: A computer-readable recording medium having stored therein a program for causing a computer to execute a digital signature process, wherein the digital signature process includes distributing packets to machines based on session durations according to a communication of the packets in a given duration, and performing verification tests based on the packets distributed to the machines by each of the machines.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: March 31, 2015
    Assignee: Fijitsu Limited
    Inventors: Takeshi Yasuie, Taichi Sugiyama, Yuji Nomura
  • Publication number: 20150023371
    Abstract: A mismatch detecting method includes: specifying a configuration of test data in accordance with a condition in which a time when a first packet out of a plurality of packets included in the test data caused to make a round trip through a transmission path including a plurality of sections is transmitted in one section out of the plural sections in an inbound path and a time when a second packet out of the plural packets is transmitted in the one section in an outbound path overlap with each other; transmitting the test data to the transmission path in accordance with the configuration specified by the specifying; and determining a mismatch of a transmission system within the transmission path, based on a loss situation of the test data returning from the transmission path after the transmitting.
    Type: Application
    Filed: June 19, 2014
    Publication date: January 22, 2015
    Applicant: Fujitsu Limited
    Inventors: Takeshi Yasuie, Yuji Nomura
  • Publication number: 20150003457
    Abstract: An information processing apparatus includes a processor configured to perform a process which includes determining an address available to be set as a source address of a first packet to be transmitted to an apparatus included in a network; identifying one or more relay apparatuses in a communication route from the apparatus to the information processing apparatus; and configuring, for at least one of the identified relay apparatuses, a setting regarding a transfer destination of a second packet whose destination address is the determined address in such a manner that the second packet is transferred toward the information processing apparatus along the communication route.
    Type: Application
    Filed: April 9, 2014
    Publication date: January 1, 2015
    Inventors: Taichi SUGIYAMA, Takeshi Yasuie, Yuji Nomura
  • Publication number: 20140365446
    Abstract: A verification system include: a server that receives each of a first data group and second data group, and transmits a third data group and a fourth data group to respond to each of the first data group and second data group received; a database server that receives the third data group and transmits the second data group; and a verification device that performs operation verification of the server or database server, the verification device including a processor configured to transmit, to the database server, a partial data group in the third data group received by the database server, and transmit, to the server, the first data group corresponding to another data group in the third data group, thereby supplying the other data group to the database server and using the first data group, the partial data group, and the fourth data group, to perform the operation verification.
    Type: Application
    Filed: May 23, 2014
    Publication date: December 11, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Taichi Sugiyama, Takeshi Yasuie, Yuji Nomura
  • Publication number: 20140297767
    Abstract: An information processing apparatus obtains a plurality of messages transmitted between a client and a server, each message including at least one of a plurality of parameters and a value of the parameter. The information processing apparatus detects a parameter having different values set in different messages among the obtained plurality of messages, from among the plurality of parameters. According to the detection result, the information processing apparatus determines a rewrite parameter whose value is rewritten when using the plurality of messages for verification of a server, among the plurality of parameters.
    Type: Application
    Filed: March 21, 2014
    Publication date: October 2, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi YASUIE, Taichi SUGIYAMA
  • Publication number: 20140189009
    Abstract: A computer is disclosed that performs a verification process. The computer analyzes quality characteristics of communication for each of predetermined quality analysis subjects from actual capture data. The computer generates send data based on the actual capture data and an exchanging message which is acquired when a reproduced operation is verified based on the actual capture data. The computer sends the send data to a verification subject apparatus at sending timing based on the quality characteristics. The computer receives response data from the verification subject apparatus. The computer verifies an operation of the verification subject apparatus.
    Type: Application
    Filed: November 1, 2013
    Publication date: July 3, 2014
    Applicant: Fujitsu Limited
    Inventors: Takeshi YASUIE, Taichi SUGIYAMA, Yuji NOMURA
  • Patent number: 8724502
    Abstract: A computer-readable medium stores a testing program that causes a computer having a storage device storing netmask lengths and address block utilization information associated with address blocks, to execute a process that includes acquiring first packets transmitted to a first apparatus, first addresses being regarded as transmission sources; referring to the storage device and acquiring a count of address blocks to which the first addresses belong and a netmask length; calculating based on the acquired address block count and netmask length, the netmask length less a bit count according to the number of the first addresses; referring to the storage device and selecting from among unused address blocks, an address block having a netmask length less than or equal to the calculated netmask length; and transmitting to a second apparatus, second packets obtained by setting the transmission sources of the first packets to second addresses in the selected address block.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: May 13, 2014
    Assignee: Fujitsu Limited
    Inventors: Taichi Sugiyama, Takeshi Yasuie, Yuji Nomura
  • Patent number: 8706838
    Abstract: A testing apparatus includes a storage to store a communication log including a communication time and a response confirmation number of packets, and a processing circuit to generate an additional packet having a communication time and a response confirmation number between two consecutive packets having an interval greater than or equal to a threshold value in the communication log. The interval may be an interval of the communication times of or, an interval of the response confirmation numbers of the two consecutive packets. The testing apparatus also includes an interface unit to send the packets stored in the storage and the additional packet to a destination at a time interval based on communication times thereof.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: April 22, 2014
    Assignee: Fujitsu Limited
    Inventors: Taichi Sugiyama, Takeshi Yasuie, Yuji Nomura
  • Patent number: 8593997
    Abstract: A full duplex/half duplex mismatch is detected by a full duplex/half duplex mismatch detecting apparatus connected through a network to a host. The loss rate of the transmission of a check messages is compared according to a sequential transmission pattern and the loss rate of the transmission of the check message according to divided transmission patterns by the full duplex/half duplex mismatch detecting apparatus, and if the loss rate of the transmission of the check messages according to the sequential transmission pattern is the larger, a full duplex/half duplex mismatch is determined to be present on the network path.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: November 26, 2013
    Assignee: Fujitsu Limited
    Inventors: Yuji Nomura, Takeshi Yasuie
  • Patent number: 8595571
    Abstract: An error detection device includes a control unit configured to identify two links that connects a relay communication device to two communication devices as a link pair, identify, from pluralities of inspection devices under the respective two links, a number of inspection devices corresponding to the number N of links where communication errors simultaneously occur (N is an integer of 1 or more) plus 1, determine (N+1) number of inspection flows between the (N+1) number of inspection device pairs, and generate inspection coverage information that includes the determined inspection flows. The error detection device includes a storage unit that stores the inspection coverage information, and a communication unit that sends the inspection coverage information to one device of the inspection device pairs.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: November 26, 2013
    Assignee: Fujitsu Limited
    Inventors: Takeshi Yasuie, Yuji Nomura