Abstract: A semiconductor memory device is provided which is capable of initializing the data values stored in memory cells in a shorter time without increasing the size of a chip. The semiconductor memory device comprises memory cells arranged at the intersection of word lines and data lines; a level setting circuit which sets the levels of the data lines to a predetermined initialization level when an initialization signal, which is activated when the data values stored in the memory cells are initialized, is activated; a delay circuit which delays the initialization signal to generate delayed initialization signals, each of which corresponds to one of the word lines and the delay times thereof differ from each other; and a logic circuit which sets the level of one of the word lines corresponding to one of the delayed initialization signals to an activation level when the corresponding delayed initialization signal is activated.

Abstract: A fast-response semiconductor memory which can avoid noises from over-macro through wiring affecting macro wiring and reduce the parasitic capacitance appearing on the macro wiring as well. The semiconductor memory has a shield layer between RAM macro wiring inside a macro and through wiring over the macro. The shield layer has a plurality of conductive layers arranged parallel to each other at a pitch of W1, the conductive layers extending in the direction orthogonal to the RAM macro wiring. For an appropriate length of the RAM macro wiring, this shield layer is provided so that the pitch W1 of the conductive layers is equal to or smaller than P1, where P1 is a pitch of the conductive layers at which the interlayer capacitance between the RAM macro wiring and the shield layer becomes equal to the interlayer capacitance between the RAM macro wiring and the over-macro through wiring.

Abstract: A semiconductor memory device is provided which is capable of initializing the data values stored in memory cells in a shorter time without increasing the size of a chip. The semiconductor memory device comprises memory cells arranged at the intersection of word lines and data lines; a level setting circuit which sets the levels of the data lines to a predetermined initialization level when an initialization signal, which is activated when the data values stored in the memory cells are initialized, is activated; a delay circuit which delays the initialization signal to generate delayed initialization signals, each of which corresponds to one of the word lines and the delay times thereof differ from each other; and a logic circuit which sets the level of one of the word lines corresponding to one of the delayed initialization signals to an activation level when the corresponding delayed initialization signal is activated.