Abstract: A synchronizer has a 1-field memory and a reset signal generator. The reset signal generator receives a write sync. signal to control the 1-field memory and outputs a write reset signal which adjusts the timing for writing according to a read sync. signal. An image signal written into the 1-field memory in accordance with the timing determined by the write reset signal is thus synchronized with the timing for reading.

Abstract: A video image displaying system comprises first video equipment for converting a HDTV video signal to a plurality of video signals of a second format for display on a plurality of television receivers responsive to signals of the second format and second video equipment for providing one or more video signals of the second format to selected television receivers in response to a switching circuit. The image displaying system includes a noise reduction circuit, with coring circuit, in which the characteristics of first and second filters are set in such a way as their overall characteristic becomes flat so as to reduce a noise overlapping a high frequency range of a video signal. The image displaying system further includes a synchronizing signal generator which provides a phase difference between synchronizing signals to be supplied to a first and second video equipments, thus compensating for a delay time of the high definition television signal encountered in an image dividing unit.