Patents by Inventor Taketo Kunihisa

Taketo Kunihisa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7692470
    Abstract: A level conversion circuit according to the present invention comprises: a first transistor having a gate thereof grounded, for inputting the input voltage to a source thereof and outputting an output voltage from a drain thereof; a second transistor having a drain thereof to which a power supply voltage is applied, for inputting the output voltage outputted from the drain of the first transistor to a gate thereof and outputting, from a source thereof, the output voltage determined by the power supply voltage; a level shift circuit for inputting the output voltage outputted from the source of the second transistor to an input end thereof and outputting, from an output end thereof, a voltage whose level is shifted by a predetermined amount; and a resistance inserted between the output end of the level shift circuit and a ground. Thus, it becomes possible to reduce a current Ii flowing to the gate of the first transistor to a level close to zero.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: April 6, 2010
    Assignee: Panasonic Corporation
    Inventors: Shinji Yamamoto, Toshihiko Takeda, Taketo Kunihisa
  • Publication number: 20090033402
    Abstract: A level conversion circuit according to the present invention comprises: a first transistor having a gate thereof grounded, for inputting the input voltage to a source thereof and outputting an output voltage from a drain thereof; a second transistor having a drain thereof to which a power supply voltage is applied, for inputting the output voltage outputted from the drain of the first transistor to a gate thereof and outputting, from a source thereof, the output voltage determined by the power supply voltage; a level shift circuit for inputting the output voltage outputted from the source of the second transistor to an input end thereof and outputting, from an output end thereof, a voltage whose level is shifted by a predetermined amount; and a resistance inserted between the output end of the level shift circuit and a ground. Thus, it becomes possible to reduce a current Ii flowing to the gate of the first transistor to a level close to zero.
    Type: Application
    Filed: July 29, 2008
    Publication date: February 5, 2009
    Inventors: Shinji Yamamoto, Toshihiko Takeda, Taketo Kunihisa
  • Publication number: 20070085592
    Abstract: In a high-frequency switch circuit having a booster circuit and a voltage switch circuit for ON/OFF control of the booster circuit, the voltage switch circuit has a means for gradually dropping the gate input voltage and the drain/source input voltage of a series of FETs over a voltage drop time of 10 ?sec or more at the time of switching from a boosted voltage to a non-boosted voltage.
    Type: Application
    Filed: September 11, 2006
    Publication date: April 19, 2007
    Inventors: Eiji Yasuda, Tadayoshi Nakatsuka, Toshihiro Shougaki, Kenichi Hidaka, Taketo Kunihisa
  • Patent number: 6756683
    Abstract: A semiconductor device includes a silicon substrate with a resistivity being raised by diffusing Au etc. therein, and includes both active elements and passive elements. The active elements are all placed within a semiconductor chip, and the semiconductor chip is flip-chip mounted over the silicon substrate. Such a case where the silicon substrate is heated due to a heating process for forming the active elements can be avoided, and therefore, diffusion of Au etc. from the silicon substrate into the semiconductor device can be avoided.
    Type: Grant
    Filed: April 15, 2002
    Date of Patent: June 29, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Taketo Kunihisa, Toshihide Nobusada, Kazuhiro Yahata
  • Patent number: 6489843
    Abstract: A power amplifier including: a first amplifier PA2 having an input terminal and an output terminal; a passive circuit PC3 having an input terminal and an output terminal; and a first switch SW2 having a single-pole terminal and two multi-throw terminals, one of the multi-throw terminals of the first switch SW2 being connected to the input terminal of the first amplifier PA2 and the other of the multi-throw terminals of the first switch SW2 being connected to the input terminal of the passive circuit PC3. This makes it possible to provide a power amplifier and a communication unit which can be operated with different frequencies, output powers or modulation types.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: December 3, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaaki Nishijima, Taketo Kunihisa, Osamu Ishikawa
  • Publication number: 20020153616
    Abstract: A semiconductor device includes a silicon substrate with a resistivity being raised by diffusing Au etc. therein, and includes both active elements and passive elements. The active elements are all placed within a semiconductor chip, and the semiconductor chip is flip-chip mounted over the silicon substrate. Such a case where the silicon substrate is heated due to a heating process for forming the active elements can be avoided, and therefore, diffusion of Au etc. from the silicon substrate into the semiconductor device can be avoided.
    Type: Application
    Filed: April 15, 2002
    Publication date: October 24, 2002
    Inventors: Taketo Kunihisa, Toshihide Nobusada, Kazuhiro Yahata
  • Patent number: 6313700
    Abstract: A power amplifier including: a first amplifier PA2 having an input terminal and an output terminal; a passive circuit PC3 having an input terminal and an output terminal; and a first switch SW2 having a single-pole terminal and two multi-throw terminals, one of the multi-throw terminals of the first switch SW2 being connected to the input terminal of the first amplifier PA2 and the other of the multi-throw terminals of the first switch SW2 being connected to the input terminal of the passive circuit PC3. This makes it possible to provide a power amplifier and a communication unit which can be operated with different frequencies, output powers or modulation types.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: November 6, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaaki Nishijima, Taketo Kunihisa, Osamu Ishikawa
  • Patent number: 6313699
    Abstract: A power amplifier including: a first amplifier PA2 having an input terminal and an output terminal; a passive circuit PC3 having an input terminal and an output terminal; and a first switch SW2 having a single-pole terminal and two multi-throw terminals, one of the multi-throw terminals of the first switch SW2 being connected to the input terminal of the first amplifier PA2 and the other of the multi-throw terminals of the first switch SW2 being connected to the input terminal of the passive circuit PC3. This makes it possible to provide a power amplifier and a communication unit which can be operated with different frequencies, output powers or modulation types.
    Type: Grant
    Filed: June 13, 2000
    Date of Patent: November 6, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaaki Nishijima, Taketo Kunihisa, Osamu Ishikawa
  • Patent number: 6111459
    Abstract: A power amplifier including: a first amplifier PA2 having an input terminal and an output terminal; a passive circuit PC3 having an input terminal and an output terminal; and a first switch SW2 having a single-pole terminal and two multi-throw terminals, one of the multi-throw terminals of the first switch SW2 being connected to the input terminal of the first amplifier PA2 and the other of the multi-throw terminals of the first switch SW2 being connected to the input terminal of the passive circuit PC3. This makes it possible to provide a power amplifier and a communication unit which can be operated with different frequencies, output powers or modulation types.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: August 29, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaaki Nishijima, Taketo Kunihisa, Osamu Ishikawa
  • Patent number: 6046501
    Abstract: An RF-driven semiconductor chip is die-bonded to the top face of a metal plate. The semiconductor chip and the metal plate are molded together with outer leads in a plastic package in the form of a rectangular parallelepiped. The metal plate is exposed at the back face of the plastic package. The metal plate is not protruding from the front and rear side faces of the plastic package. The front and rear side faces of the metal plate are flush with the front and rear side faces of the plastic package and partially exposed at the front and rear side faces of the plastic package. The front and rear portions of the plastic package are centrally formed with respective cutaway portions each in the form of a rectangular parallelepiped. The top face of the metal plate is exposed in the cutaway portions formed centrally in the front and rear portions of the plastic package to form solder portions.
    Type: Grant
    Filed: October 1, 1997
    Date of Patent: April 4, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Osamu Ishikawa, Takahiro Yokoyama, Taketo Kunihisa, Masaaki Nishijima, Shinji Yamamoto, Junji Itoh, Toshio Fujiwara, Kaoru Muramatsu
  • Patent number: 5982236
    Abstract: A high-frequency power amplifier comprises a transistor for high-frequency power which operates and whose current-voltage characteristics greatly change when positive voltage is supplied on its input terminal, an input bias circuit, an output bias circuit, an input impedance matching circuit, an output impedance matching circuit, and a positive voltage generation circuit. The positive voltage generation circuit comprises a detection circuit which detects part of the high-frequency power which is entered to or outputted from the transistor for high-frequency power, a rectification circuit which rectifies the part of the high-frequency power outputted from the detection circuit and outputs pulsating positive voltage, and a smoothing circuit which smoothes the pulsating positive voltage outputted from the rectification circuit and outputs positive voltage.
    Type: Grant
    Filed: January 20, 1998
    Date of Patent: November 9, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Osamu Ishikawa, Takahiro Yokoyama, Taketo Kunihisa, Junji Ito, Masaaki Nishijima, Shinji Yamamoto
  • Patent number: 5461265
    Abstract: A variable impedance element suitable for controlling a high-frequency signal is formed of a pair of FETs of identical conduction type, and functions to prevent variations in degree of channel opening of the FETs in response to positive and negative-going changes of the controlled signal voltage, to thereby achieve high linearity of impedance characteristics. Each FET has the drain and gate electrodes mutually coupled by a capacitor, the source electrodes of the FETs are mutually coupled, the gate electrodes are mutually isolated with respect to the high-frequency signal and coupled in common to receive an impedance control voltage, and the variable impedance appears between the drain electrodes.
    Type: Grant
    Filed: April 30, 1993
    Date of Patent: October 24, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Taketo Kunihisa, Tadayoshi Nakatsuka
  • Patent number: 5319318
    Abstract: A gain control circuit includes a first FET for serving as an active load, a second FET serving as an amplifier, and a third FET for serving as a current source. The first, second, and third FETs have substantially the same characteristics and are mutually connected in a series. The gain control circuit further includes a fourth FET for serving as a variable active load connected in parallel with the third FET and a capacitor connected between the third and fourth FETs. The fourth FET is also connected to a gain control terminal. The gain of the second FET is controlled by the voltage applied to the gate of the fourth FET through said gain control line.
    Type: Grant
    Filed: August 18, 1992
    Date of Patent: June 7, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Taketo Kunihisa, Yukio Sakai, Kazuhiro Yahata, Tadayoshi Nakatsuka, Hideki Yagita
  • Patent number: 5210504
    Abstract: A semiconductor device for a tuner capable of simultaneously satisfying a low noise factor, low third order distortion characteristics and low power consumption, and a tuner using this semiconductor device for a tuner and capable of reducing the size and eliminating labor during assembly. The semiconductor device is a variable gain amplification circuit comprising a gate grounded circuit using a transistor, and a differential amplification circuit including transistors and constant current sources. Transistors are used as variable resistance devices, and the gain of the gate grounded circuit can be varied by changing the gate voltage of a transistor. The gain of the differential amplification circuit can be varied by changing the gate voltage of another transistor. The overall gain of the circuit can be varied within a necessary range by simultaneously operating these gain controls, and the third order distortion can be improved monotonously with the decrease of the gain.
    Type: Grant
    Filed: March 16, 1992
    Date of Patent: May 11, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideki Yagita, Tadayoshi Nakatsuka, Taketo Kunihisa, Michiaki Tsuneoka, Yukio Sakai, Kazuhiro Yahata