Patents by Inventor Taketoshi Itoyama

Taketoshi Itoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5614837
    Abstract: A loader section for supplying semiconductor wafers is arranged at one end of a linear first convey path for a convey unit. Burn-in test sections, probe test sections, a laser repair section, a deposition repair section, a marking section, a baking section, and visual test sections are arranged on both the sides of the first convey path. In the burn-in test section arranged in the loader section, each semiconductor wafer picked up from a cassette is pre-aligned. The pre-aligned semiconductor wafers are loaded/unloaded into/from the respective test sections and the repair section by the convey unit in accordance with a predetermined test procedure, thereby performing a plurality of test items and repair steps by an inline scheme. Each burn-in test section includes a probe card having conductive projections which are brought into contact with all of many semiconductor chips formed on each semiconductor wafer at once.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: March 25, 1997
    Assignee: Tokyo Electron Limited
    Inventors: Taketoshi Itoyama, Yuichi Abe, Masao Yamaguchi
  • Patent number: 5510724
    Abstract: A loader section for supplying semiconductor wafers is arranged at one end of a linear first convey path for a convey unit. Burn-in test sections, probe test sections, a laser repair section, a deposition repair section, a marking section, a baking section, and visual test sections are arranged on both the sides of the first convey path. In the burn-in test section arranged in the loader section, each semiconductor wafer picked up from a cassette is pre-aligned. The pre-aligned semiconductor wafers are loaded/unloaded into/from the respective test sections and the repair section by the convey unit in accordance with a predetermined test procedure, thereby performing a plurality of test items and repair steps by an inline scheme. Each burn-in test section includes a probe card having conductive projections which are brought into contact with all of many semiconductor chips formed on each semiconductor wafer at once.
    Type: Grant
    Filed: May 31, 1994
    Date of Patent: April 23, 1996
    Assignee: Tokyo Electron Limited
    Inventors: Taketoshi Itoyama, Yuichi Abe, Masao Yamaguchi
  • Patent number: 5172053
    Abstract: A proper apparatus includes a test head for generating a test signal. A probe card is fixed removably on the test head. The probe card supplies the test signal to a test piece when the probe card electrically contacts the test piece, and tests electric characteristics of the test piece.
    Type: Grant
    Filed: July 1, 1991
    Date of Patent: December 15, 1992
    Assignee: Tokyo Electron Limited
    Inventor: Taketoshi Itoyama
  • Patent number: 5086270
    Abstract: A probe apparatus having a measuring section with a first system for electrically measuring an object. A loader section has a second system for carrying objects to the measuring section and a marking section has a third system for marking objects. These sections are independent of each other so that a vibration occurring in one section is not transmitted to the other sections.
    Type: Grant
    Filed: December 31, 1990
    Date of Patent: February 4, 1992
    Assignee: Tokyo Electron Limited
    Inventors: Wataru Karasawa, Taketoshi Itoyama, Itaru Takao, Tadashi Obikane, Hisashi Koike