Patents by Inventor Taketoshi Matsuura
Taketoshi Matsuura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6659352Abstract: A semiconductor integrated circuit which obtains a driving power from a carrier onto which data has been piggybacked, the semiconductor integrated circuit being characterized by demodulating data by correctly discriminating it even when the obtained power supply voltage has become overvoltage, and characterized by effectively using the power supplied by the carrier. The semiconductor integrated circuit includes: a two-voltage rectifier circuit as a power source circuit 111; a voltage regulator circuit 112 which exercises a control so that a power with a higher voltage (VDDH) used for demodulating data does not exceed a certain voltage value; a resistor 141; and a capacitor 142. With this construction, the voltage input to a regulator circuit 1121 as the reference voltage changes in correspondence to the change in voltage VDDH which is caused by the change in amplitude.Type: GrantFiled: May 31, 2000Date of Patent: December 9, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroaki Asada, Joji Nakane, Tatsumi Sumi, Taketoshi Matsuura, Atsuo Inoue
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Publication number: 20030030041Abstract: The infrared reflector of the present invention has an infrared-reflecting layer and an infrared-permeable layer which is formed on the infrared-reflecting layer. The infrared-reflecting layer has a reflectance of 60% or more and a permeability of 25% or less with respect to infrared rays having a wavelength within a range of 800 to 1600 nanometers. The infrared-permeable layer has a reflectance of less than 60% and an absorbance of 50% or less with respect to infrared rays having a wavelength within a range of 800 to 1600 nanometers. The infrared-permeable layer contains resin components and pigments, and the amount of carbon black contained in the infrared-permeable layer is 0.1 wt % or less. This infrared reflector can provide various coloration that includes dark colors while maintaining the high infrared reflectivity on the whole.Type: ApplicationFiled: April 12, 2002Publication date: February 13, 2003Inventors: Yasuhiro Genjima, Haruhiko Mochizuki, Taketoshi Matsuura
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Patent number: 6462115Abstract: A water repellent coating composition includes fine particles having functional groups on their surfaces and having a particle diameter ranging from 10 nm to 1 mm; a coupling agent containing (a) a functional group which is capable of reacting with the functional group of the fine particles and (b) a water repellent fluorinated group; a binder resin for binding the fine particles; and a solvent for the binder.Type: GrantFiled: August 15, 1997Date of Patent: October 8, 2002Assignees: Nippon Telegraph and Telephone Corporation, NTT Advanced Technology CorporationInventors: Masaya Takahashi, Susumu Fujimori, Mamoru Ishitani, Taketoshi Matsuura, Hisao Tabei, Yoshiaki Haga, Akira Nohara, Nobuhiro Funakoshi
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Patent number: 6333528Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.Type: GrantFiled: May 4, 1998Date of Patent: December 25, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
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Patent number: 6294438Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.Type: GrantFiled: June 8, 2000Date of Patent: September 25, 2001Assignee: Matsushita Electronics CorporationInventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
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Patent number: 6169304Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.Type: GrantFiled: May 4, 1998Date of Patent: January 2, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
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Patent number: 6107657Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.Type: GrantFiled: May 4, 1998Date of Patent: August 22, 2000Assignee: Matsushita Electronics CorporationInventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
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Patent number: 6044795Abstract: An automatic feeding system includes a tag attached to a body of a pet; and an automatic feeding apparatus for automatically feeding the pet. The tag includes a receiving device for receiving an electromagnetic wave from the automatic feeding apparatus; an information memory device storing information on the feeding of the pet and outputting the information in response to an output from the receiving device; and a sending device for sending the information which is output from the information memory device to the automatic feeding apparatus using an electric wave.Type: GrantFiled: June 30, 1998Date of Patent: April 4, 2000Assignee: Matsushita Electronics CorporationInventors: Taketoshi Matsuura, Eiji Fujii, Kazuhiro Mori
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Patent number: 6033920Abstract: This invention relates to a semiconductor device with embedded capacitor elements of which capacitor insulation layer is made of ferroelectric layer or dielectric layer of high dielectric constant, and its manufacturing method. This invention is made in order to solve the problems of rapid increase of leak current of capacitor element and the poor reliability caused by the large deviation of crystal sizes of conventional capacitor insulation layer of capacitor element incorporated in the semiconductor device.Type: GrantFiled: July 24, 1998Date of Patent: March 7, 2000Assignee: Matsushita Electronics CorporationInventors: Yasuhiro Shimada, Yasuhiro Uemoto, Atsuo Inoue, Taketoshi Matsuura, Masamichi Azuma
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Patent number: 6015987Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.Type: GrantFiled: May 4, 1998Date of Patent: January 18, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
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Patent number: 5828098Abstract: This invention relates to a semiconductor device with embedded capacitor elements of which capacitor insulation layer is made of ferroelectric layer or dielectric layer of high dielectric constant, and its manufacturing method. This invention is made in order to solve the problems of rapid increase of leak current of capacitor element and the poor reliability caused by the large deviation of crystal sizes of conventional capacitor insulation layer of capacitor element incorporated in the semiconductor device.Type: GrantFiled: June 20, 1996Date of Patent: October 27, 1998Assignee: Matsushita Electronics CorporationInventors: Yasuhiro Shimada, Yasuhiro Uemoto, Atsuo Inoue, Taketoshi Matsuura, Masamichi Azuma
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Patent number: 5780351Abstract: A semi conductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.Type: GrantFiled: April 28, 1997Date of Patent: July 14, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
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Patent number: 5624864Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.Type: GrantFiled: August 4, 1994Date of Patent: April 29, 1997Assignee: Matsushita Electronics CorporationInventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
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Patent number: 5479111Abstract: In a signal transmitting device in a semiconductor apparatus, a second signal 29 and a third signal 40 are activated by the activation of a first signal 2 which is entered. More specifically, the third signal 40 is firstly activated, and the second signal 29 is then activated while the third signal 40 is being activated, and then the third signal 40 is inactivated. Further, a fourth signal 42 is activated by the activation of the second signal 29 or by the activation of the third signal 40. Accordingly, even though a noise removing circuit 80 or the like is disposed in a first signal transmitting circuit 70 for activating the second signal 29, the period of time required by the time the fourth signal 42 is activated, can be shortened. Thus, there can be obtained a semiconductor apparatus which is fast in access (speed at which a signal is transmitted to a subsequent stage) and which is resistant to noise.Type: GrantFiled: July 14, 1994Date of Patent: December 26, 1995Assignee: Matsushita Electronics CorporationInventor: Taketoshi Matsuura