Patents by Inventor Taketoshi Nakamura

Taketoshi Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10562264
    Abstract: An object of the present invention is to provide a waterproof moisture-permeable fabric suppressed in appearance abnormality and deterioration in barrier properties. A waterproof moisture-permeable fabric including a protective layer and a polyethylene microporous film that are stacked on each other with a synthetic rubber-based hot-melt adhesive, an olefinic hot-melt adhesive, or a composite hot-melt adhesive interposed therebetween, having a nonpolar oil content of 2 g/m2 or less, and a polar oil content of 0.01 g/m2 or more and 6 g/m2 or less.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: February 18, 2020
    Assignee: TORAY INDUSTRIES, INC.
    Inventors: Taketoshi Nakamura, Yuichiro Hayashi, Masanobu Takeda
  • Publication number: 20180099476
    Abstract: An object of the present invention is to provide a waterproof moisture-permeable fabric suppressed in appearance abnormality and deterioration in barrier properties. A waterproof moisture-permeable fabric including a protective layer and a polyethylene microporous film that are stacked on each other with a synthetic rubber-based hot-melt adhesive, an olefinic hot-melt adhesive, or a composite hot-melt adhesive interposed therebetween, having a nonpolar oil content of 2 g/m2 or less, and a polar oil content of 0.01 g/m2 or more and 6 g/m2 or less.
    Type: Application
    Filed: April 27, 2016
    Publication date: April 12, 2018
    Applicant: TORAY INDUSTRIES, INC.
    Inventors: Taketoshi NAKAMURA, Yuichiro HAYASHI, Masanobu TAKEDA
  • Publication number: 20170326485
    Abstract: The present invention provides a protective clothing having high dust proof property which prevents powder dust from entering into the clothing and having high air permeability for comfortable work, in which the temperature does not rise easily even in summer. A dust-proof clothing using the following dust-proof material, wherein i) the dust-proof material has a fiber layer and an electret nonwoven fabric layer, and a total number of the fiber layer and the electret nonwoven fabric layer is 2 or more; and ii) in the dust-proof material, the fiber layer and the electret nonwoven fabric layer, which are adjacent to each other, are adhered on a region having an area ratio of 5% or more and 10% or less.
    Type: Application
    Filed: December 22, 2015
    Publication date: November 16, 2017
    Applicant: TORAY INDUSTRIES, INC.
    Inventors: Taketoshi NAKAMURA, Hiroshi KAJIYAMA, Yuichiro HAYASHI, Masanobu TAKEDA
  • Patent number: 7728445
    Abstract: A semiconductor device production method which includes steps of: preparing a wafer on which multiple integrated circuits are formed on a principal face; forming a rewiring which is electrically connected to the integrated circuits via a pad electrode; and dicing the wafer after forming an electrode terminal on the rewiring, including steps of: forming a first resin layer by sealing at least the rewiring and the electrode terminal formed on the principal face of the wafer with a first resin; processing a first dicing from a back face of the wafer to the principal face of the wafer or halfway to the first resin layer when the first resin layer is formed; forming a second resin layer by sealing a cut line outlined upon the first dicing and the back face of the wafer continuously with a first resin; and processing a second dicing while leaving the second resin layer which covers a side face outlined upon the first dicing.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: June 1, 2010
    Assignee: Yamaha Corporation
    Inventors: Taketoshi Nakamura, Hiroshi Saitoh
  • Publication number: 20060244149
    Abstract: A semiconductor device production method which includes steps of: preparing a wafer on which multiple integrated circuits are formed on a principal face; forming a rewiring which is electrically connected to the integrated circuits via a pad electrode; and dicing the wafer after forming an electrode terminal on the rewiring, including steps of: forming a first resin layer by sealing at least the rewiring and the electrode terminal formed on the principal face of the wafer with a first resin; processing a first dicing from a back face of the wafer to the principal face of the wafer or halfway to the first resin layer when the first resin layer is formed; forming a second resin layer by sealing a cut line outlined upon the first dicing and the back face of the wafer continuously with a first resin; and processing a second dicing while leaving the second resin layer which covers a side face outlined upon the first dicing.
    Type: Application
    Filed: March 15, 2006
    Publication date: November 2, 2006
    Inventors: Taketoshi Nakamura, Hiroshi Saitoh