Patents by Inventor Taketoshi Tanaka
Taketoshi Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240106962Abstract: An image reading device includes a reading unit that reads an image on a surface of a medium; and a calibrating unit that is disposed to face the reading unit with the medium disposed therebetween and that calibrates the reading unit. The calibrating unit is supported such that the calibrating unit is movable about a rotating shaft between a closing position at which the calibrating unit faces the reading unit and an opening position at which the calibrating unit is separated from the reading unit. The calibrating unit is positioned with respect to the reading unit when the calibrating unit is moved to the closing position.Type: ApplicationFiled: March 23, 2023Publication date: March 28, 2024Applicant: FUJIFILM Business Innovation Corp.Inventors: Masakazu SHIRAI, Taketoshi TANAKA, Akio SHIMONAGA, Masaaki TAKENOUCHI, Takuma AYABE
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Patent number: 11923128Abstract: An electronic component includes an insulating layer, a low voltage conductor pattern formed inside the insulating layer, a high voltage conductor pattern formed inside the insulating layer such as to face the low voltage conductor pattern in an up/down direction, and a withstand voltage enhancement structure of conductive property formed inside the insulating layer and along the high voltage conductor pattern such as to protrude further outside than the low voltage conductor pattern in plan view.Type: GrantFiled: December 6, 2022Date of Patent: March 5, 2024Assignee: ROHM CO., LTD.Inventors: Taketoshi Tanaka, Kosei Osada, Masahiko Arimura
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Patent number: 11899390Abstract: A recording-material-transporting apparatus includes: a transport unit that transports a recording material along a transport path; an image reading unit that is disposed on one side of the transport path and that reads an image formed on the recording material transported along the transport path; and a rotating member disposed opposite the image reading unit with the transport path provided therebetween. At least one portion of the rotating member contacts the image reading unit, or a rotating member support that supports the rotating member contacts the image reading unit.Type: GrantFiled: September 9, 2022Date of Patent: February 13, 2024Assignee: FUJIFILM Business Innovation Corp.Inventors: Seiichi Takayama, Masakazu Shirai, Taketoshi Tanaka, Tadashi Sugizaki
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Publication number: 20230303349Abstract: A recording-material-transporting apparatus includes: a transport unit that transports a recording material along a transport path; at least one image reader that reads an image formed on the recording material transported by the transport unit; and a common housing that supports the transport unit and the at least one image reader. The transport path is accessible by a user through at least one gap existing between the transport path and the at least one image reader.Type: ApplicationFiled: September 13, 2022Publication date: September 28, 2023Applicant: FUJIFILM Business Innovation Corp.Inventors: Masakazu SHIRAI, Taketoshi TANAKA
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Publication number: 20230305473Abstract: A recording-material-transporting apparatus includes: a transport unit that transports a recording material along a transport path; an image reading unit that is disposed on one side of the transport path and that reads an image formed on the recording material transported along the transport path; and a rotating member disposed opposite the image reading unit with the transport path provided therebetween. At least one portion of the rotating member contacts the image reading unit, or a rotating member support that supports the rotating member contacts the image reading unit.Type: ApplicationFiled: September 9, 2022Publication date: September 28, 2023Applicant: FUJIFILM BUSINESS INNOVATION CORP.Inventors: Seiichi TAKAYAMA, Masakazu SHIRAI, Taketoshi TANAKA, Tadashi SUGIZAKI
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Patent number: 11769825Abstract: Provided is a nitride semiconductor device 3 including a GaN electron transit layer 13, an AlGaN electron supply layer 14 in contact with the electron transit layer 13, a gate layer 15, formed selectively on the electron supply layer 14 and constituted of a nitride semiconductor composition effectively not containing an acceptor type impurity, and a gate electrode 16, formed on the gate layer 15, and satisfying the following formula (1): d g ? 2 ? E F ? q ? ( N DA + N A - N DD - N D ) ? 0 ? ? C + ? B - d B ? P ? 0 ? ? C > 0.Type: GrantFiled: December 10, 2021Date of Patent: September 26, 2023Assignee: ROHM CO., LTD.Inventor: Taketoshi Tanaka
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Publication number: 20230114315Abstract: A nitride semiconductor device includes an electron transit layer, an electron supply layer that is formed on the electron transit layer, a gate layer that is formed on the electron supply layer and contains an Al1-xGaxN (0 < × < 1) based material containing a first impurity, a gate electrode that is formed on the gate layer and is in Schottky junction with the gate layer, and a source electrode and a drain electrode that are electrically connected to the electron supply layer. By this arrangement, a gate withstand voltage can be improved and therefore, a nitride semiconductor device of high reliability can be provided.Type: ApplicationFiled: April 14, 2021Publication date: April 13, 2023Inventors: Norikazu ITO, Taketoshi TANAKA, Ken NAKAHARA
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Publication number: 20230107689Abstract: An electronic component includes an insulating layer, a low voltage conductor pattern formed inside the insulating layer, a high voltage conductor pattern formed inside the insulating layer such as to face the low voltage conductor pattern in an up/down direction, and a withstand voltage enhancement structure of conductive property formed inside the insulating layer and along the high voltage conductor pattern such as to protrude further outside than the low voltage conductor pattern in plan view.Type: ApplicationFiled: December 6, 2022Publication date: April 6, 2023Inventors: Taketoshi TANAKA, Kosei OSADA, Masahiko ARIMURA
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Publication number: 20230074009Abstract: A capacitor includes a substrate 2 that has a first principal surface at one side and a second principal surface at another side, a plurality of first internal electrode forming penetrating holes 3 that penetrate through the substrate in a thickness direction, a plurality of second internal electrode forming penetrating holes 4 that penetrate through the substrate in the thickness direction, first internal electrodes 5 that are constituted of conductors embedded inside the first internal electrode forming penetrating holes, and second internal electrodes 6 that are constituted of conductors embedded inside the second internal electrode forming penetrating holes. The plurality of internal electrode forming penetrating holes 3 and 4 that include the plurality of first internal electrode forming penetrating holes 3 and the plurality of second internal electrode forming penetrating holes 4 are disposed in a lattice in a plan view as viewed from a normal direction orthogonal to the first principal surface.Type: ApplicationFiled: December 9, 2020Publication date: March 9, 2023Applicant: ROHM CO., LTD.Inventors: Ryosuke ISHIDO, Taketoshi TANAKA
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Patent number: 11545299Abstract: An electronic component includes an insulating layer, a low voltage conductor pattern formed inside the insulating layer, a high voltage conductor pattern formed inside the insulating layer such as to face the low voltage conductor pattern in an up/down direction, and a withstand voltage enhancement structure of conductive property formed inside the insulating layer and along the high voltage conductor pattern such as to protrude further outside than the low voltage conductor pattern in plan view.Type: GrantFiled: October 15, 2018Date of Patent: January 3, 2023Assignee: ROHM CO., LTD.Inventors: Taketoshi Tanaka, Kosei Osada, Masahiko Arimura
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Publication number: 20220302262Abstract: A nitride semiconductor device includes a first impurity layer made of an Al1-XGaXN (0<X?1) based material and containing a first impurity with which a depth of an acceptor level from a valence band (ET-EV) is made not less than 0.3 eV but less than 0.6 eV, an electron transit layer formed on the first impurity layer, an electron supply layer formed on the electron transit layer, agate electrode formed on the electron transit layer, and a source electrode and a drain electrode formed such that the source electrode and the drain electrode sandwich the gate electrode and electrically connected to the electron supply layer.Type: ApplicationFiled: June 7, 2022Publication date: September 22, 2022Inventors: Norikazu ITO, Taketoshi TANAKA, Ken NAKAHARA
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Patent number: 11393905Abstract: A nitride semiconductor device includes a first impurity layer made of an Al1-XGaXN (0<X?1) based material and containing a first impurity with which a depth of an acceptor level from a valence band (ET-EV) is made not less than 0.3 eV but less than 0.6 eV, an electron transit layer formed on the first impurity layer, an electron supply layer formed on the electron transit layer, agate electrode formed on the electron transit layer, and a source electrode and a drain electrode formed such that the source electrode and the drain electrode sandwich the gate electrode and electrically connected to the electron supply layer.Type: GrantFiled: December 21, 2018Date of Patent: July 19, 2022Assignee: ROHM CO., LTD.Inventors: Norikazu Ito, Taketoshi Tanaka, Ken Nakahara
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Publication number: 20220223725Abstract: A semiconductor device (1) includes a substrate (2), an electron transit layer (4) disposed on the substrate (2), and an electron supply layer (5) disposed on the electron supply layer (4). The electron transit layer (4) includes a conductive path forming layer (43) in contact with the electron supply layer (5), a first semiconductor region (first nitride semiconductor layer) (41) containing an acceptor-type impurity, and a second semiconductor region (second nitride semiconductor layer) (42) disposed at a position closer to the conductive path forming layer (43) than the first semiconductor region (41) and containing an acceptor-type impurity. The first semiconductor region (41) has a higher acceptor density than the second semiconductor region (42).Type: ApplicationFiled: March 29, 2022Publication date: July 14, 2022Inventor: Taketoshi TANAKA
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Patent number: 11316041Abstract: A semiconductor device (1) includes a substrate (2), an electron transit layer (4) disposed on the substrate (2), and an electron supply layer (5) disposed on the electron supply layer (4). The electron transit layer (4) includes a conductive path forming layer (43) in contact with the electron supply layer (5), a first semiconductor region (first nitride semiconductor layer) (41) containing an acceptor-type impurity, and a second semiconductor region (second nitride semiconductor layer) (42) disposed at a position closer to the conductive path forming layer (43) than the first semiconductor region (41) and containing an acceptor-type impurity. The first semiconductor region (41) has a higher acceptor density than the second semiconductor region (42).Type: GrantFiled: November 13, 2018Date of Patent: April 26, 2022Assignee: ROHM CO., LTD.Inventor: Taketoshi Tanaka
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Patent number: 11296193Abstract: A nitride semiconductor device 1 includes a first nitride semiconductor layer 4, constituting an electron transit layer, a second nitride semiconductor layer 5, formed on the first nitride semiconductor layer 4 and constituting an electron supply layer, a nitride semiconductor gate layer 6, disposed on the second nitride semiconductor layer 5 and containing an acceptor type impurity, a metal film 7, formed on the nitride semiconductor gate layer 6, and a gate pad 23, connected to the metal film 7 via a gate insulating film 8 having a first surface and a second surface, the first surface of the gate insulating film 8 is electrically connected directly or via a metal to the metal film 7, and the second surface of the gate insulating film 8 is electrically connected directly or via a metal to the gate pad 23.Type: GrantFiled: January 16, 2019Date of Patent: April 5, 2022Assignee: ROHM CO., LTD.Inventor: Taketoshi Tanaka
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Publication number: 20220102543Abstract: A nitride semiconductor device 1 includes a first nitride semiconductor layer 4 that constitutes an electron transit layer, a second nitride semiconductor layer 5 that is formed on the first nitride semiconductor layer, is larger in bandgap than the first nitride semiconductor layer, and constitutes an electron supply layer, and a gate portion 20 that is formed on the second nitride semiconductor layer. The gate portion 20 includes a first semiconductor gate layer 21 of a ridge shape that is disposed on the second nitride semiconductor layer 5 and is constituted of a nitride semiconductor containing an acceptor type impurity, a second semiconductor gate layer 22 that is formed on the first semiconductor gate layer 21 and is constituted of a nitride semiconductor with a larger bandgap than the first semiconductor gate layer 21, and a gate electrode 23 that is formed on the second semiconductor gate layer 22 and is in Schottky junction with the second semiconductor gate layer 22.Type: ApplicationFiled: January 15, 2020Publication date: March 31, 2022Inventors: Hirotaka OTAKE, Shinya TAKADO, Taketoshi TANAKA, Norikazu ITO
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Publication number: 20220102545Abstract: Provided is a nitride semiconductor device 3 including a GaN electron transit layer 13, an AlGaN electron supply layer 14 in contact with the electron transit layer 13, a gate layer 15, formed selectively on the electron supply layer 14 and constituted of a nitride semiconductor composition effectively not containing an acceptor type impurity, and a gate electrode 16, formed on the gate layer 15, and satisfying the following formula (1): d g ? 2 ? E F ? q ? ( N DA + N A - N DD - N D ) ? 0 ? ? C + ? B - d B ? P ? 0 ? ? C > 0 ( 1 )Type: ApplicationFiled: December 10, 2021Publication date: March 31, 2022Inventor: Taketoshi TANAKA
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Patent number: 11233144Abstract: Provided is a nitride semiconductor device 3 including a GaN electron transit layer 13, an AlGaN electron supply layer 14 in contact with the electron transit layer 13, a gate layer 15, formed selectively on the electron supply layer 14 and constituted of a nitride semiconductor composition effectively not containing an acceptor type impurity, and a gate electrode 16, formed on the gate lever 15, and satisfying the following formula (1): d G ? 2 ? E F ? q ? ( N DA + N A - N DD - N D ) ? 0 ? ? C + ? B - d B ? P ? 0 ? ? B > 0 ( 1 )Type: GrantFiled: May 7, 2019Date of Patent: January 25, 2022Assignee: ROHM CO., LTD.Inventor: Taketoshi Tanaka
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Publication number: 20210193380Abstract: An electronic component includes an insulating layer, a low voltage conductor pattern formed inside the insulating layer, a high voltage conductor pattern formed inside the insulating layer such as to face the low voltage conductor pattern in an up/down direction, and a withstand voltage enhancement structure of conductive property formed inside the insulating layer and along the high voltage conductor pattern such as to protrude further outside than the low voltage conductor pattern in plan view.Type: ApplicationFiled: October 15, 2018Publication date: June 24, 2021Inventors: Taketoshi TANAKA, Kosei OSADA, Masahiko ARIMURA
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Publication number: 20200365694Abstract: A nitride semiconductor device includes a first impurity layer made of an Al1-XGaXN (0<X?1) based material and containing a first impurity with which a depth of an acceptor level from a valence band (ET-EV) is made not less than 0.3 eV but less than 0.6 eV, an electron transit layer formed on the first impurity layer, an electron supply layer formed on the electron transit layer, agate electrode formed on the electron transit layer, and a source electrode and a drain electrode formed such that the source electrode and the drain electrode sandwich the gate electrode and electrically connected to the electron supply layer.Type: ApplicationFiled: December 21, 2018Publication date: November 19, 2020Inventors: Norikazu ITO, Taketoshi TANAKA, Ken NAKAHARA