Abstract: Disclosed is a semiconductor device having a multilayer wiring structure, in which a dummy pattern is formed in a wiring void with favorable manufacturing efficiency. In a semiconductor device having a multilayer wiring structure, dummy pattern (21) is formed in relatively narrow wiring void (Area_S1) so as to extend in a direction different from that of dummy patterns (22, 23) formed in relatively wide wiring void (Area_S2).

Abstract: Disclosed is a semiconductor device having a multilayer wiring structure, in which a dummy pattern is formed in a wiring void with favorable manufacturing efficiency. In a semiconductor device having a multilayer wiring structure, dummy pattern (21) is formed in relatively narrow wiring void (Area_S1) so as to extend in a direction different from that of dummy patterns (22, 23) formed in relatively wide wiring void (Area_S2).

Abstract: A semiconductor device including a plurality of cells having an antenna protection element and a cell other than the antenna protection element; and a first dummy pattern and a second dummy pattern arranged in a layer above the plurality of cells. Further, the first dummy pattern overlaps with the antenna protection element, the second dummy pattern overlaps with the cell other than the antenna protection element, and a first layout rule of the first dummy pattern is different from a second layout rule of the second dummy pattern.

Abstract: As a method for considering the adverse influence of the stresses caused form the pad, two sorts of methods are provided. As one method, while delay variation values of cells caused by an adverse influence of stresses are calculated, the calculated delay variation values are applied to the cells so as to perform a timing analysis, and the like by considering the adverse influence of the stresses. Then, in order that a flip chip type LSI is designed by employing a result of the above-described analysis in such a manner that the adverse influence of the stresses applied from the pad is not given to vias, wiring lines, and cells located under the pad, such a physical structure that no via is arranged under the pad is employed.

Abstract: In each wiring layer in which wirings connected to a gate is formed, wirings are routed so as not to cover the active region of an antenna protection element. A wiring formed in an upper wiring layer is routed so as to cover at least a part of the active region of the antenna protection element.

Abstract: Prevention of coming off of the layer where the contacts are formed and the isolating film and breakage of the LSI is realized. To do this, a contact array is provided in which a plurality of contacts is formed so as to be aligned in the vertical and the horizontal directions. In the contact array, the contact formation spacing in both of the vertical and the horizontal directions is larger than the contact formation spacing determined by the manufacturing process. Consequently, the number of contacts formed in the contact array can be reduced to not more than the number of contacts that can be formed in the unit area determined by the process, so that prevention of coming off of the layer where the contacts are formed and the isolating film and breakage of the LSI can be realized.

Abstract: Prevention of coming off of the layer where the contacts are formed and the isolating film and breakage of the LSI is realized. To do this, a contact array is provided in which a plurality of contacts is formed so as to be aligned in the vertical and the horizontal directions. In the contact array, the contact formation spacing in both of the vertical and the horizontal directions is larger than the contact formation spacing determined by the manufacturing process. Consequently, the number of contacts formed in the contact array can be reduced to not more than the number of contacts that can be formed in the unit area determined by the process, so that prevention of coming off of the layer where the contacts are formed and the isolating film and breakage of the LSI can be realized.