Patents by Inventor Takeya Motonobu

Takeya Motonobu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9299828
    Abstract: A nitride-based transistor includes a semiconductor structure, a gate electrode and a leakage current suppression structure. The semiconductor structure includes a first nitride-based semiconductor layer doped with impurities of a first conductivity type, a second nitride-based semiconductor layer doped with impurities of a second conductivity type, and a third nitride-based semiconductor layer doped with impurities of the first conductivity type. The gate electrode overlaps the second nitride-based semiconductor layer. The leakage current suppression structure is disposed along edges of the semiconductor structure. The leakage current suppression structure includes a depletion layer in at least one of the first and third nitride-based semiconductor layers.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: March 29, 2016
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventor: Takeya Motonobu
  • Publication number: 20150162428
    Abstract: A nitride-based transistor includes a semiconductor structure, a gate electrode and a leakage current suppression structure. The semiconductor structure includes a first nitride-based semiconductor layer doped with impurities of a first conductivity type, a second nitride-based semiconductor layer doped with impurities of a second conductivity type, and a third nitride-based semiconductor layer doped with impurities of the first conductivity type. The gate electrode overlaps the second nitride-based semiconductor layer. The leakage current suppression structure is disposed along edges of the semiconductor structure. The leakage current suppression structure includes a depletion layer in at least one of the first and third nitride-based semiconductor layers.
    Type: Application
    Filed: December 2, 2014
    Publication date: June 11, 2015
    Inventor: Takeya MOTONOBU
  • Publication number: 20150060943
    Abstract: A method of fabricating a nitride-based transistor includes sequentially forming a first nitride-based semiconductor layer doped with first type dopant, a second nitride-based semiconductor layer doped with at least one of a second type dopant, and a third nitride-based semiconductor layer doped with at least one of the first type dopants. A first trench is formed to penetrate the third and second nitride-based semiconductor layers and to extend into the first nitride-based semiconductor layer. A fourth nitride-based semiconductor layer doped with the first type dopants is formed to fill the first trench. A second trench is formed in the fourth nitride-based semiconductor layer. A gate electrode is formed in the second trench. A source electrode is formed to be electrically connected to at least one of the third and fourth nitride-based semiconductor layers, and a drain electrode is formed to be electrically connected to the first nitride-based semiconductor layer.
    Type: Application
    Filed: August 27, 2014
    Publication date: March 5, 2015
    Inventors: Takeya MOTONOBU, Kwan Hyun Lee, Eun Hee Kim
  • Publication number: 20150014699
    Abstract: A vertical transistor includes a drain electrode disposed on a first region of a substrate, a drift layer disposed on a second region of the substrate spaced apart from the first region, and P-type gallium nitride current barrier layers disposed on the drift layer and comprising a current aperture disposed between current barrier layers. A channel layer is disposed on the drift layer and the current barrier layers. A semiconductor layer is disposed on the channel layer and configured to induce formation of a two-dimension electron gas layer adjacent to a top surface thereof. Metal contact plugs are disposed in the channel layer and contact the current barrier layers. A source electrode is disposed on the contact plugs and the channel layer. A gate insulation layer and a gate electrode are sequentially disposed on a top surface of the semiconductor layer opposite to the channel layer.
    Type: Application
    Filed: July 9, 2014
    Publication date: January 15, 2015
    Inventors: Takeya Motonobu, Kwan Hyun Lee, Young Do Jeong
  • Patent number: 8927302
    Abstract: Provided are a CVD apparatus and a method of manufacturing a light emitting device using the same. The CVD apparatus includes a chamber body including a susceptor having at least one pocket part having a wafer stably mounted therein; a chamber cover provided with the chamber body to open or close the chamber body and having a reaction space between the susceptor and the chamber cover; a reactive gas supplier supplying the reactive gas into the reaction space to allow the reactive gas to flow across a surface of the susceptor; and a non-reactive gas supplier supplying a non-reactive gas into the reaction space to allow the non-reactive gas to flow across a surface of the chamber cover between the susceptor and the chamber cover so as to prevent the reactive gas from contacting the surface of the chamber cover.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun Woo Kim, Takeya Motonobu, In Hoe Hur, Choo Ho Kim, Jae Bong Lee
  • Publication number: 20130260488
    Abstract: Provided are a CVD apparatus and a method of manufacturing a light emitting device using the same. The CVD apparatus includes a chamber body including a susceptor having at least one pocket part having a wafer stably mounted therein; a chamber cover provided with the chamber body to open or close the chamber body and having a reaction space between the susceptor and the chamber cover; a reactive gas supplier supplying the reactive gas into the reaction space to allow the reactive gas to flow across a surface of the susceptor; and a non-reactive gas supplier supplying a non-reactive gas into the reaction space to allow the non-reactive gas to flow across a surface of the chamber cover between the susceptor and the chamber cover so as to prevent the reactive gas from contacting the surface of the chamber cover.
    Type: Application
    Filed: December 20, 2011
    Publication date: October 3, 2013
    Applicant: Samsung Electronics Co., LTD.
    Inventors: Jun Woo Kim, Takeya Motonobu, In Hoe Hur, Choo Ho Kim, Jae Bong Lee