Patents by Inventor Takio Yamashita

Takio Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6903453
    Abstract: A semiconductor integrated circuit device includes: a first semiconductor chip including a CPU and a debug basic circuit section for verifying operation of a program executed by the CPU; and a second semiconductor chip retained over a principal surface of the first semiconductor chip and including a debug extension circuit section electrically connected to the CPU and the debug basic circuit section. The debug basic circuit section includes a debug command analyzing section for analyzing a command input from outside. The debug extension circuit section formed in the second semiconductor chip includes a debugging function circuit section including at least one debug circuit.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: June 7, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Motohide Nishibata, Tsutomu Mikami, Atsushi Ubukata, Takio Yamashita, Kouichirou Miyawaki
  • Publication number: 20040255199
    Abstract: The present invention provides a debug system in which both a debug operation for a microprocessor and security of information stored in the debug system are achieved.
    Type: Application
    Filed: March 17, 2004
    Publication date: December 16, 2004
    Inventor: Takio Yamashita
  • Publication number: 20040019826
    Abstract: A semiconductor integrated circuit device includes: a first semiconductor chip including a CPU and a debug basic circuit section for verifying operation of a program executed by the CPU; and a second semiconductor chip retained over a principal surface of the first semiconductor chip and including a debug extension circuit section electrically connected to the CPU and the debug basic circuit section. The debug basic circuit section includes a debug command analyzing section for analyzing a command input from outside. The debug extension circuit section formed in the second semiconductor chip includes a debugging function circuit section including at least one debug circuit.
    Type: Application
    Filed: July 18, 2003
    Publication date: January 29, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Motohide Nishibata, Tsutomu Mikami, Atsushi Ubukata, Takio Yamashita, Kouichirou Miyawaki
  • Patent number: 5821625
    Abstract: The present invention reduces crosstalk, which occurs as a result of interference between signals running in each of respective wiring layers of a first semiconductor chip and a second semiconductor chip stacked surface to surface with a small gap. The semiconductor device includes a first semiconductor chip 1 having a first electrode pad 2 and a first wiring layer 9 in the main surface, and a second semiconductor chip 5 having a second electrode pad 6 and a second wiring layer 10 in the main surface confronting the first semiconductor chip. A bump 4 is provided for electrically coupling the first electrode pad 2 and the second electrode pad 6 together. An insulation layer 8 is disposed between the main surfaces of first semiconductor chip 1 and second semiconductor chip 5. An electro-conductive layer 7 is disposed between the main confronting surfaces of the first semiconductor chip and the second semiconductor chip.
    Type: Grant
    Filed: April 23, 1996
    Date of Patent: October 13, 1998
    Assignees: Matsushita Electric Industrial Co., Ltd., Matsushita Electronics Corp.
    Inventors: Takayuki Yoshida, Takashi Otsuka, Hiroaki Fujimoto, Tadaaki Mimura, Ichiro Yamane, Takio Yamashita, Toshio Matsuki, Yoshiaki Kasuga
  • Patent number: 5805865
    Abstract: A microcomputer chip is formed with a CPU core, a peripheral circuit, a built-in ROM, and a built-in RAM. An emulation functional chip is formed with an emulation control circuit for controlling the whole process of emulation. First electrode pads formed on the functional surface of the microcomputer chip are electrically interconnected to second electrode pads formed on the functional surface of the emulation functional chip with connecting bumps interposed therebetween. The microcomputer chip and the emulation functional chip are modularized using an insulating resin with the first electrode pads being connected to the second electrode pads.
    Type: Grant
    Filed: September 26, 1996
    Date of Patent: September 8, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tadaaki Mimura, Takayuki Yoshida, Ichiro Yamane, Takio Yamashita, Toshio Matsuki, Yoshiaki Kasuga, Hiroaki Fujimoto
  • Patent number: 5767009
    Abstract: The present invention reduces crosstalk noise, which occurs as a result of interference between signals running in each of respective wiring layers of a first semiconductor chip and a second semiconductor chip stacked surface to surface with a small gap. The semiconductor device includes a first semiconductor chip (1) having a first electrode pad (2) and a first wiring layer (9), and a second semiconductor chip (5) having a second electrode pad (6) and a second wiring layer (10). A bump (4) is provided for electrically coupling the first electrode pad (2) and the second electrode pad (6). An insulation layer 8 is disposed between confronting surfaces of the first semiconductor chip (1) and the second semiconductor chip (5). An electro-conductive layer (7) is disposed between the confronting surfaces of the first semiconductor chip and the second semiconductor chip.
    Type: Grant
    Filed: February 10, 1997
    Date of Patent: June 16, 1998
    Assignees: Matsushita Electric Industrial Co., Ltd., Matsushita Electronics Corp.
    Inventors: Takayuki Yoshida, Takashi Otsuka, Hiroaki Fujimoto, Tadaaki Mimura, Ichiro Yamane, Takio Yamashita, Toshio Matsuki, Yoshiaki Kasuga