Patents by Inventor Taku KAWAMURA

Taku KAWAMURA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for verifying circuit design
    Patent number: 9547568
    Abstract: A verification test is performed on a device containing master and slave units connected via a bus. In the verification test, a first signal is transferred between a first master unit and a first slave unit during a first transfer period while a second signal is transferred between a second master unit and a second slave unit during a second transfer period. The second transfer period overlaps at least a part of the first transfer period. When the first transfer period is longer than a third transfer period, first combination information indicating the combination of the first master unit and first slave unit is stored in a storage unit, in conjunction with second combination information indicating the combination of the second master unit and second slave unit.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: January 17, 2017
    Assignee: SOCIONEXT INC.
    Inventor: Taku Kawamura
  • METHOD AND APPARATUS FOR VERIFYING CIRCUIT DESIGN
    Publication number: 20140214355
    Abstract: A verification test is performed on a device containing master and slave units connected via a bus. In the verification test, a first signal is transferred between a first master unit and a first slave unit during a first transfer period while a second signal is transferred between a second master unit and a second slave unit during a second transfer period. The second transfer period overlaps at least a part of the first transfer period. When the first transfer period is longer than a third transfer period, first combination information indicating the combination of the first master unit and first slave unit is stored in a storage unit, in conjunction with second combination information indicating the combination of the second master unit and second slave unit.
    Type: Application
    Filed: December 19, 2013
    Publication date: July 31, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Taku KAWAMURA