Patents by Inventor Taku Sato
Taku Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11958301Abstract: A printing apparatus includes a printing unit configured to print an image on a print medium, an acquiring unit configured to acquire temperature information of the printing unit, and a control unit configured to control the printing unit so as to start relative scanning in a case where a temperature that is indicated by the temperature information has reached a print permission temperature. The print permission temperature in a first print mode whose speed at a time of a constant speed in relative scanning is a first speed is a first temperature. The print permission temperature in a second print mode whose speed at the time of the constant speed is a second speed that is faster than the first speed is a second temperature that is lower than the first temperature.Type: GrantFiled: June 23, 2021Date of Patent: April 16, 2024Assignee: Canon Kabushiki KaishaInventors: Takeshi Murase, Kazuhiko Sato, Taku Yokozawa, Noboru Kunimine, Hiroshi Taira, Hiroshi Kawafuji, Sae Mogi, Akiko Aichi
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Patent number: 11952441Abstract: A method for producing polytetrafluoroethylene, which includes polymerizing tetrafluoroethylene in an aqueous medium in the presence of a nucleating agent and a hydrocarbon anionic surfactant to obtain polytetrafluoroethylene. A total amount of the nucleating agent and the hydrocarbon anionic surfactant at the initiation of polymerization is more than 50 ppm based on the aqueous medium.Type: GrantFiled: October 3, 2019Date of Patent: April 9, 2024Assignee: DAIKIN INDUSTRIES, LTD.Inventors: Taketo Kato, Yohei Fujimoto, Kenji Ichikawa, Hiroyuki Sato, Yoshinori Nanba, Hirotoshi Yoshida, Kengo Ito, Chiaki Okui, Masamichi Sukegawa, Taku Yamanaka
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Publication number: 20240106712Abstract: A network node apparatus (SMF) responsible for a Session Management Function (SMF) in a core network includes: an obtaining unit configured to obtain network function information including information elements respectively related to network slices supported by the SMF; and a first communication processing unit configured to transmit the network function information to a network node apparatus responsible for a Network Repository Function (NRF) in the core network. The information elements respectively related to the network slices supported by the SMF have been aggregated within the network function information according to a predetermined rule.Type: ApplicationFiled: September 13, 2023Publication date: March 28, 2024Applicant: NEC CorporationInventors: Yusuke TAMURA, Toshihiro IKEDA, Taku SATO
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Publication number: 20240084931Abstract: A profile for a fenestration system includes a first portion and a second portion offset from the first portion and thereby defining an inner space therebetween. The profile for a fenestration system further includes a retention mechanism arranged within the inner space, and one or more communication lines mounted to the retention mechanism.Type: ApplicationFiled: June 19, 2023Publication date: March 14, 2024Applicant: ARCONIC TECHNOLOGIES LLCInventors: Lester Taku SATO, Fraser LEWINS, Jeremy DAVIES, Ion-Horatiu BARBULESCU
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Publication number: 20240085539Abstract: A LIDAR device includes a transmission unit, a scanning unit, a reception unit, a data conversion unit, a data holding unit, a frequency analysis unit configured to execute frequency analysis to acquire ranging point data, and a point group generator configured to generate a group of ranging points acquired by using a result of frequency analysis on a first analysis target data set and a group of ranging points acquired by using a result of frequency analysis on a second analysis target data set.Type: ApplicationFiled: June 20, 2023Publication date: March 14, 2024Inventors: Masashige SATO, Taku SUZUKI
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Patent number: 11919321Abstract: A printing apparatus includes a printing unit configured to print an image on a print medium, an acquiring unit configured to acquire temperature information of the printing unit, and a control unit configured to control the printing unit so as to start relative scanning in a case where a temperature that is indicated by the temperature information has reached a print permission temperature. The print permission temperature in a first print mode whose speed at a time of a constant speed in relative scanning is a first speed is a first temperature. The print permission temperature in a second print mode whose speed at the time of the constant speed is a second speed that is faster than the first speed is a second temperature that is lower than the first temperature.Type: GrantFiled: June 23, 2021Date of Patent: March 5, 2024Assignee: Canon Kabushiki KaishaInventors: Takeshi Murase, Kazuhiko Sato, Taku Yokozawa, Noboru Kunimine, Hiroshi Taira, Hiroshi Kawafuji, Sae Mogi, Akiko Aichi
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Patent number: 10734508Abstract: A compound semiconductor device includes a first transistor formed on a GaN epitaxial layer. The first transistor includes a gate electrode, a source electrode, a drain electrode, and a protective film covering them. End portions of the first transistor do not overhang the protective film, and the concentration of fluorine in the GaN epitaxial layer in the region where the gate electrode of the first transistor is formed is substantially zero.Type: GrantFiled: September 20, 2017Date of Patent: August 4, 2020Assignee: ADVANTEST CORPORATIONInventors: Jun'ichi Okayasu, Taku Sato
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Patent number: 10229912Abstract: According to the present invention, a semiconductor device includes a semiconductor layer, a source electrode provided in the semiconductor layer, a drain electrode provided in the semiconductor layer and disposed away from the source electrode, a first gate electrode provided between the source electrode and the drain electrode and a second gate electrode provided between the source electrode and the drain electrode, the second gate electrode having at least a part thereof located closer to the drain electrode than the first gate electrode. The semiconductor layer includes a first facing part that is a part facing the first gate electrode; and a second facing part that is a part facing the second gate electrode. The first facing part does not conduct when a first gate voltage is 0 V or less. The second facing part does not conduct when a second gate voltage is 0 V or less.Type: GrantFiled: April 18, 2016Date of Patent: March 12, 2019Assignee: ADVANTEST CORPORATIONInventors: Taku Sato, Kazuya Uryu, Kazuyuki Shouji
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Patent number: 10115802Abstract: A support substrate is bonded to a GaN epitaxial substrate including at least an electron transport layer and an electron supply layer grown on a growth substrate in the Ga-polar direction such that the support substrate faces the Ga-plane of the GaN epitaxial substrate. Furthermore, at least the growth substrate is removed from the GaN epitaxial substrate so as to expose an N-plane of the GaN epitaxial substrate. Subsequently, a semiconductor element is formed on the N-plane side.Type: GrantFiled: May 10, 2017Date of Patent: October 30, 2018Assignee: ADVANTEST CORPORATIONInventor: Taku Sato
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Publication number: 20180151568Abstract: According to the present invention, a semiconductor device includes a semiconductor layer, a source electrode provided in the semiconductor layer, a drain electrode provided in the semiconductor layer and disposed away from the source electrode, a first gate electrode provided between the source electrode and the drain electrode and a second gate electrode provided between the source electrode and the drain electrode, the second gate electrode having at least a part thereof located closer to the drain electrode than the first gate electrode. The semiconductor layer includes a first facing part that is a part facing the first gate electrode; and a second facing part that is a part facing the second gate electrode. The first facing part does not conduct when a first gate voltage is 0 V or less. The second facing part does not conduct when a second gate voltage is 0 V or less.Type: ApplicationFiled: April 18, 2016Publication date: May 31, 2018Applicant: ADVANTEST CORPORATIONInventors: Taku SATO, Kazuya URYU, Kazuyuki SHOUJI
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Publication number: 20180138302Abstract: A compound semiconductor device includes a first transistor formed on a GaN epitaxial layer. The first transistor includes a gate electrode, a source electrode, a drain electrode, and a protective film covering them. End portions of the first transistor do not overhang the protective film, and the concentration of fluorine in the GaN epitaxial layer in the region where the gate electrode of the first transistor is formed is substantially zero.Type: ApplicationFiled: September 20, 2017Publication date: May 17, 2018Inventors: Jun'ichi OKAYASU, Taku SATO
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Publication number: 20170365667Abstract: A GaN epitaxial substrate comprises a growth substrate and a multilayer structure grown on the growth substrate in the Ga-polar direction. The multilayer structure comprises: a buffer layer, an n-type conductive layer formed on the buffer layer, a first GaN layer formed on the n-type conductive layer, an electron supply layer formed on the first GaN layer, and a second GaN layer formed on the electron supply layer.Type: ApplicationFiled: May 10, 2017Publication date: December 21, 2017Inventor: Taku SATO
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Publication number: 20170365689Abstract: A support substrate is bonded to a GaN epitaxial substrate including at least an electron transport layer and an electron supply layer grown on a growth substrate in the Ga-polar direction such that the support substrate faces the Ga-plane of the GaN epitaxial substrate. Furthermore, at least the growth substrate is removed from the GaN epitaxial substrate so as to expose an N-plane of the GaN epitaxial substrate. Subsequently, a semiconductor element is formed on the N-plane side.Type: ApplicationFiled: May 10, 2017Publication date: December 21, 2017Inventor: Taku SATO
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Patent number: 9639037Abstract: An image forming apparatus includes: an image forming unit configured to form a toner image on a paper sheet; a fixing unit configured to fix the toner image onto the paper sheet; a fixing temperature detecting unit configured to detect a fixing temperature in the fixing unit; and a control unit configured to allow a fixing operation in the fixing unit only after the fixing temperature is adjusted to be within a predetermined allowable fixing temperature range, when the fixing temperature is outside the allowable fixing temperature range, wherein the control unit sets the allowable fixing temperature range in accordance with fixing properties required in an output of a pattern image for adjustment in an adjustment mode in which various kinds of adjustments related to image formation can be performed based on an output of the pattern image for adjustment.Type: GrantFiled: December 2, 2014Date of Patent: May 2, 2017Assignee: KONICA MINOLTA, INC.Inventor: Taku Sato
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Publication number: 20170098494Abstract: Methods and apparatus for manufacturing a conductive thin film are provided. In one arrangement, compositions of nanowires having different mean aspect ratios are mixed together and applied as a layer on a substrate. In other arrangements a single composition of nanowires is processed in order to increase an aspect ratio variance and the processed composition is applied as a layer on a substrate. The layers thus applied provide an improved balance of electrical conductivity to transparency and are expected to provide improved isotropy in the inplane conductivity.Type: ApplicationFiled: May 11, 2015Publication date: April 6, 2017Applicant: M-SOLV LIMITEDInventors: Alan Brian DALTON, Lester Taku SATO, Matthew LARGE, Philip Thomas RUMSBY
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Patent number: 9584114Abstract: A semiconductor switch is configured to conduct or cutoff a signal path from its first terminal to its second terminal. An enhancement-type first transistor is arranged between the first terminal and the second terminal. A first bias circuit is connected to apply a gate voltage VG that corresponds to a control signal VCNT to the gate of the first transistor when the power supply voltages VDD and VSS are supplied. A second bias circuit is connected such that a voltage that corresponds to the lower voltage of the voltages at the first terminal and the second terminal is applied to the gate of the first transistor when the power supply voltages VDD and VSS are not supplied.Type: GrantFiled: June 3, 2015Date of Patent: February 28, 2017Assignee: ADVANTEST CORPORATIONInventors: Yoshiyuki Hata, Taku Sato, Masahiko Takikawa
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Patent number: 9434936Abstract: A method for separating cells which includes: adhering cells to the surface of a cell culture substrate containing a photo-acid generator that generates an acidic substance upon irradiation with active energy rays, and irradiating only a partial region of the cell culture substrate with the active energy rays to selectively remove the cells within the partial region, thereby separating the cells within the partial region and cells in other regions.Type: GrantFiled: March 28, 2011Date of Patent: September 6, 2016Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Kimio Sumaru, Toshiyuki Takagi, Kyoko Kikuchi, Taku Sato, Manae Yamaguchi, Toshiyuki Kanamori
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Publication number: 20160020765Abstract: A semiconductor switch is configured to conduct or cutoff a signal path from its first terminal to its second terminal. An enhancement-type first transistor is arranged between the first terminal and the second terminal. A first bias circuit is connected to apply a gate voltage VG that corresponds to a control signal VCNT to the gate of the first transistor when the power supply voltages VDD and VSS are supplied. A second bias circuit is connected such that a voltage that corresponds to the lower voltage of the voltages at the first terminal and the second terminal is applied to the gate of the first transistor when the power supply voltages VDD and VSS are not supplied.Type: ApplicationFiled: June 3, 2015Publication date: January 21, 2016Applicant: ADVANTEST CORPORATIONInventors: Yoshiyuki HATA, Taku SATO, Masahiko TAKIKAWA
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Publication number: 20150168887Abstract: An image forming apparatus includes: an image forming unit configured to forma toner image on a paper sheet; a fixing unit configured to fix the toner image onto the paper sheet; a fixing temperature detecting unit configured to detect a fixing temperature in the fixing unit; and a control unit configured to allow a fixing operation in the fixing unit only after the fixing temperature is adjusted to be within a predetermined allowable fixing temperature range, when the fixing temperature is outside the allowable fixing temperature range, wherein the control unit sets the allowable fixing temperature range in accordance with fixing properties required in an output of a pattern image for adjustment in an adjustment mode in which various kinds of adjustments related to image formation can be performed based on an output of the pattern image for adjustment.Type: ApplicationFiled: December 2, 2014Publication date: June 18, 2015Applicant: KONICA MINOLTA INC.Inventor: Taku SATO
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Patent number: 8466566Abstract: It is an objective to provide a semiconductor device with low leak current. The semiconductor device includes a plurality of ground side electrodes and a plurality of signal side electrodes arranged on a semiconductor substrate in an alternating manner; a plurality of control electrodes arranged respectively between each pair of a ground side electrode and a signal side electrode; a ground side electrode connecting section that connects the ground side electrodes to each other; a signal side electrode connecting section that connects the signal side electrodes to each other; and ground side lead wiring and signal side lead wiring that extend respectively from a region near one end and a region near another end of an arranged electrode section, in which the ground side electrodes and the signal side electrodes are arranged in an arrangement direction, away from the arranged electrode group in the arrangement direction.Type: GrantFiled: April 1, 2011Date of Patent: June 18, 2013Assignee: Advantest CorporationInventors: Makoto Nakanishi, Tomoo Yamanouchi, Junichi Okayasu, Taku Sato, Daiju Terasawa, Masahiko Takikawa