Patents by Inventor Taku Sato

Taku Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250251692
    Abstract: An image forming system includes: a sheet conveyance section configured to convey a rolled sheet; an image forming section configured to form an image on the rolled sheet; a winding section configured to wind the rolled sheet; and a hardware processor. The hardware processor is capable of changing a print counting position on a conveyance path between the image forming section and the winding section, the print counting position at which a print is counted based on the image formed on the rolled sheet.
    Type: Application
    Filed: February 5, 2025
    Publication date: August 7, 2025
    Inventor: Taku SATO
  • Publication number: 20250139933
    Abstract: An information processing apparatus comprises an acquisition unit configured to acquire input data, and an application unit configured to obtain an attention vector by performing a feature transformation process having a local receptive field on the input data, and apply attention to the input data based on the input data and the attention vector.
    Type: Application
    Filed: October 15, 2024
    Publication date: May 1, 2025
    Inventor: Taku SATO
  • Patent number: 12250122
    Abstract: A network node apparatus (SMF) responsible for a Session Management Function (SMF) in a core network includes: an obtaining unit configured to obtain network function information including information elements respectively related to network slices supported by the SMF; and a first communication processing unit configured to transmit the network function information to a network node apparatus responsible for a Network Repository Function (NRF) in the core network. The information elements respectively related to the network slices supported by the SMF have been aggregated within the network function information according to a predetermined rule.
    Type: Grant
    Filed: September 13, 2023
    Date of Patent: March 11, 2025
    Assignee: NEC CORPORATION
    Inventors: Yusuke Tamura, Toshihiro Ikeda, Taku Sato
  • Publication number: 20250074063
    Abstract: A liquid ejection device includes a liquid ejection head, a standby portion, a hold portion, and an operation portion. The liquid ejection head includes a nozzle surface. The standby portion supports a wiping cartridge. The hold portion holds the wiping cartridge. The operation portion moves the hold portion relatively to the standby portion and the liquid ejection head from a position at which the hold portion holds the wiping cartridge that is not held by the hold portion and that is supported by the standby portion to a position at which the wiping cartridge held by the hold portion comes into contact with the nozzle surface.
    Type: Application
    Filed: July 15, 2022
    Publication date: March 6, 2025
    Inventors: Takuya TSUTSUMI, Ryota IMANISHI, Tatsumi UWAI, Masaya KIMACHI, Taku SATO, Hiroyuki SUGIMOTO
  • Publication number: 20250068107
    Abstract: Provided is an image forming system that includes a conveyance section, an image forming section, an image reading section, a winding section, and a hardware processor. The hardware processor controls, when a plurality of print jobs is printed on one continuous recording medium held in the image forming system, conveyance by the conveyance section such that a stop position of a last image of a preceding print job on the continuous recording medium is to be a first stop position between the image reading section and the winding section, and controls, when printed on the one continuous recording medium is not a plurality of print jobs, the conveyance by the conveyance section such that the stop position of the last image on the continuous recording medium is to be a second stop position that is closer to the winding section than the first stop position.
    Type: Application
    Filed: August 21, 2024
    Publication date: February 27, 2025
    Inventor: Taku SATO
  • Publication number: 20240210341
    Abstract: A fenestration system includes opposing first and second rigid components, a gasket interposing the first and second rigid components, the gasket being made of an electrically-conductive material and exhibiting a baseline resistance when arranged between the first and second rigid components, and a control system communicably coupled to the gasket with one or more wires and operable to monitor a real-time resistance of the gasket and generate a signal when the real-time resistance deviates from the baseline resistance.
    Type: Application
    Filed: December 5, 2023
    Publication date: June 27, 2024
    Applicant: Arconic Technologies LLC
    Inventor: Lester Taku SATO
  • Publication number: 20240106712
    Abstract: A network node apparatus (SMF) responsible for a Session Management Function (SMF) in a core network includes: an obtaining unit configured to obtain network function information including information elements respectively related to network slices supported by the SMF; and a first communication processing unit configured to transmit the network function information to a network node apparatus responsible for a Network Repository Function (NRF) in the core network. The information elements respectively related to the network slices supported by the SMF have been aggregated within the network function information according to a predetermined rule.
    Type: Application
    Filed: September 13, 2023
    Publication date: March 28, 2024
    Applicant: NEC Corporation
    Inventors: Yusuke TAMURA, Toshihiro IKEDA, Taku SATO
  • Publication number: 20240084931
    Abstract: A profile for a fenestration system includes a first portion and a second portion offset from the first portion and thereby defining an inner space therebetween. The profile for a fenestration system further includes a retention mechanism arranged within the inner space, and one or more communication lines mounted to the retention mechanism.
    Type: Application
    Filed: June 19, 2023
    Publication date: March 14, 2024
    Applicant: ARCONIC TECHNOLOGIES LLC
    Inventors: Lester Taku SATO, Fraser LEWINS, Jeremy DAVIES, Ion-Horatiu BARBULESCU
  • Patent number: 10734508
    Abstract: A compound semiconductor device includes a first transistor formed on a GaN epitaxial layer. The first transistor includes a gate electrode, a source electrode, a drain electrode, and a protective film covering them. End portions of the first transistor do not overhang the protective film, and the concentration of fluorine in the GaN epitaxial layer in the region where the gate electrode of the first transistor is formed is substantially zero.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: August 4, 2020
    Assignee: ADVANTEST CORPORATION
    Inventors: Jun'ichi Okayasu, Taku Sato
  • Patent number: 10229912
    Abstract: According to the present invention, a semiconductor device includes a semiconductor layer, a source electrode provided in the semiconductor layer, a drain electrode provided in the semiconductor layer and disposed away from the source electrode, a first gate electrode provided between the source electrode and the drain electrode and a second gate electrode provided between the source electrode and the drain electrode, the second gate electrode having at least a part thereof located closer to the drain electrode than the first gate electrode. The semiconductor layer includes a first facing part that is a part facing the first gate electrode; and a second facing part that is a part facing the second gate electrode. The first facing part does not conduct when a first gate voltage is 0 V or less. The second facing part does not conduct when a second gate voltage is 0 V or less.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: March 12, 2019
    Assignee: ADVANTEST CORPORATION
    Inventors: Taku Sato, Kazuya Uryu, Kazuyuki Shouji
  • Patent number: 10115802
    Abstract: A support substrate is bonded to a GaN epitaxial substrate including at least an electron transport layer and an electron supply layer grown on a growth substrate in the Ga-polar direction such that the support substrate faces the Ga-plane of the GaN epitaxial substrate. Furthermore, at least the growth substrate is removed from the GaN epitaxial substrate so as to expose an N-plane of the GaN epitaxial substrate. Subsequently, a semiconductor element is formed on the N-plane side.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: October 30, 2018
    Assignee: ADVANTEST CORPORATION
    Inventor: Taku Sato
  • Publication number: 20180151568
    Abstract: According to the present invention, a semiconductor device includes a semiconductor layer, a source electrode provided in the semiconductor layer, a drain electrode provided in the semiconductor layer and disposed away from the source electrode, a first gate electrode provided between the source electrode and the drain electrode and a second gate electrode provided between the source electrode and the drain electrode, the second gate electrode having at least a part thereof located closer to the drain electrode than the first gate electrode. The semiconductor layer includes a first facing part that is a part facing the first gate electrode; and a second facing part that is a part facing the second gate electrode. The first facing part does not conduct when a first gate voltage is 0 V or less. The second facing part does not conduct when a second gate voltage is 0 V or less.
    Type: Application
    Filed: April 18, 2016
    Publication date: May 31, 2018
    Applicant: ADVANTEST CORPORATION
    Inventors: Taku SATO, Kazuya URYU, Kazuyuki SHOUJI
  • Publication number: 20180138302
    Abstract: A compound semiconductor device includes a first transistor formed on a GaN epitaxial layer. The first transistor includes a gate electrode, a source electrode, a drain electrode, and a protective film covering them. End portions of the first transistor do not overhang the protective film, and the concentration of fluorine in the GaN epitaxial layer in the region where the gate electrode of the first transistor is formed is substantially zero.
    Type: Application
    Filed: September 20, 2017
    Publication date: May 17, 2018
    Inventors: Jun'ichi OKAYASU, Taku SATO
  • Publication number: 20170365667
    Abstract: A GaN epitaxial substrate comprises a growth substrate and a multilayer structure grown on the growth substrate in the Ga-polar direction. The multilayer structure comprises: a buffer layer, an n-type conductive layer formed on the buffer layer, a first GaN layer formed on the n-type conductive layer, an electron supply layer formed on the first GaN layer, and a second GaN layer formed on the electron supply layer.
    Type: Application
    Filed: May 10, 2017
    Publication date: December 21, 2017
    Inventor: Taku SATO
  • Publication number: 20170365689
    Abstract: A support substrate is bonded to a GaN epitaxial substrate including at least an electron transport layer and an electron supply layer grown on a growth substrate in the Ga-polar direction such that the support substrate faces the Ga-plane of the GaN epitaxial substrate. Furthermore, at least the growth substrate is removed from the GaN epitaxial substrate so as to expose an N-plane of the GaN epitaxial substrate. Subsequently, a semiconductor element is formed on the N-plane side.
    Type: Application
    Filed: May 10, 2017
    Publication date: December 21, 2017
    Inventor: Taku SATO
  • Patent number: 9639037
    Abstract: An image forming apparatus includes: an image forming unit configured to form a toner image on a paper sheet; a fixing unit configured to fix the toner image onto the paper sheet; a fixing temperature detecting unit configured to detect a fixing temperature in the fixing unit; and a control unit configured to allow a fixing operation in the fixing unit only after the fixing temperature is adjusted to be within a predetermined allowable fixing temperature range, when the fixing temperature is outside the allowable fixing temperature range, wherein the control unit sets the allowable fixing temperature range in accordance with fixing properties required in an output of a pattern image for adjustment in an adjustment mode in which various kinds of adjustments related to image formation can be performed based on an output of the pattern image for adjustment.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: May 2, 2017
    Assignee: KONICA MINOLTA, INC.
    Inventor: Taku Sato
  • Publication number: 20170098494
    Abstract: Methods and apparatus for manufacturing a conductive thin film are provided. In one arrangement, compositions of nanowires having different mean aspect ratios are mixed together and applied as a layer on a substrate. In other arrangements a single composition of nanowires is processed in order to increase an aspect ratio variance and the processed composition is applied as a layer on a substrate. The layers thus applied provide an improved balance of electrical conductivity to transparency and are expected to provide improved isotropy in the inplane conductivity.
    Type: Application
    Filed: May 11, 2015
    Publication date: April 6, 2017
    Applicant: M-SOLV LIMITED
    Inventors: Alan Brian DALTON, Lester Taku SATO, Matthew LARGE, Philip Thomas RUMSBY
  • Patent number: 9584114
    Abstract: A semiconductor switch is configured to conduct or cutoff a signal path from its first terminal to its second terminal. An enhancement-type first transistor is arranged between the first terminal and the second terminal. A first bias circuit is connected to apply a gate voltage VG that corresponds to a control signal VCNT to the gate of the first transistor when the power supply voltages VDD and VSS are supplied. A second bias circuit is connected such that a voltage that corresponds to the lower voltage of the voltages at the first terminal and the second terminal is applied to the gate of the first transistor when the power supply voltages VDD and VSS are not supplied.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: February 28, 2017
    Assignee: ADVANTEST CORPORATION
    Inventors: Yoshiyuki Hata, Taku Sato, Masahiko Takikawa
  • Patent number: 9434936
    Abstract: A method for separating cells which includes: adhering cells to the surface of a cell culture substrate containing a photo-acid generator that generates an acidic substance upon irradiation with active energy rays, and irradiating only a partial region of the cell culture substrate with the active energy rays to selectively remove the cells within the partial region, thereby separating the cells within the partial region and cells in other regions.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: September 6, 2016
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Kimio Sumaru, Toshiyuki Takagi, Kyoko Kikuchi, Taku Sato, Manae Yamaguchi, Toshiyuki Kanamori
  • Publication number: 20160020765
    Abstract: A semiconductor switch is configured to conduct or cutoff a signal path from its first terminal to its second terminal. An enhancement-type first transistor is arranged between the first terminal and the second terminal. A first bias circuit is connected to apply a gate voltage VG that corresponds to a control signal VCNT to the gate of the first transistor when the power supply voltages VDD and VSS are supplied. A second bias circuit is connected such that a voltage that corresponds to the lower voltage of the voltages at the first terminal and the second terminal is applied to the gate of the first transistor when the power supply voltages VDD and VSS are not supplied.
    Type: Application
    Filed: June 3, 2015
    Publication date: January 21, 2016
    Applicant: ADVANTEST CORPORATION
    Inventors: Yoshiyuki HATA, Taku SATO, Masahiko TAKIKAWA