Patents by Inventor Taku SHIMOSAWA

Taku SHIMOSAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230229795
    Abstract: In a distributed ledger system including nodes of a plurality of organizations, a smart contract of a distributed ledger node of each of the organizations refers to information made open to the public in a public area, the information being related to an evidence held in a private area of each of the plurality of organizations, and in response to a trigger event of the information's meeting a given condition, executes a process of making the evidence open to the public in the public area, the evidence being held in the private area of an organization to which the smart contract belongs.
    Type: Application
    Filed: September 13, 2022
    Publication date: July 20, 2023
    Inventors: Tatsuya SATO, Taku SHIMOSAWA
  • Publication number: 20220343323
    Abstract: Method and apparatus maintaining private data with consortium blockchain is disclosed. In blockchain, a transaction is required to be verified by one or multiple nodes that are participating in the blockchain. Verification by multiple nodes is key to the immutability and consensus of the blockchain. However, when private data, which is to be disclosed to only a part of the nodes, are used in a transaction, it is likely that most or even none of the nodes can verify the transaction. The system and method disclosed herein introduces read-only organizations and allows them to serve as third-party trustful mediators to perform the necessary verification for such transactions. Through example implementations herein, the implementations can serve as a trustful third-party entity in blockchain systems and/or provide various services including auditing and integration tests in blockchain-based systems.
    Type: Application
    Filed: March 30, 2020
    Publication date: October 27, 2022
    Inventors: Taku SHIMOSAWA, Satoshi OSHIMA
  • Publication number: 20180004246
    Abstract: A problem to be solved by the present invention is, in a computer system, to reduce processing delay from wait times which occur in timer access. According to the present invention, using either a CPU core (hereinafter “processing core”) other than a CPU core which executes an application, or a DMA device, a latest timer value is always transferred from a timer device to a primary storage device. The processing core reads the transferred value upon the primary storage device instead of accessing a register of the timer device, thereby avoiding a wait which occurs when directly reading the timer value of the timer device. The transfer of the value is carried out asynchronously from the processing of the processing core, thus obviating the need for the processing core to wait for the completion of the transfer. Accordingly, it is also unnecessary for the processing core to process an interrupt or a notification from another CPU core or the DMA device.
    Type: Application
    Filed: January 23, 2015
    Publication date: January 4, 2018
    Inventors: Taku SHIMOSAWA, Hidehiro KAWAI, Hiroshi MINE, Satoshi OOSHIMA