Patents by Inventor Taku Takada

Taku Takada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5404177
    Abstract: A double-picture type television receiver for displaying two different pictures on its screen. The television receiver is equipped with an image memory having a capacity required for storing a child picture signal to be inputted, the child picture signal to be stored being for one picture and a line memory coupled in series to an output of the image memory. Also included are multipliers, one being directly coupled to the output of the image memory for multiplying the output of the image memory by a predetermined coefficient and the other being coupled to outputs of the line memory for multiplying the outputs of the line memory by a predetermined coefficient. An adder calculates the sum of outputs of the multipliers and outputs the sum signal as a child picture signal.
    Type: Grant
    Filed: October 23, 1991
    Date of Patent: April 4, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Imai, Hisashi Arita, Ryuji Matsuura, Taku Takada
  • Patent number: 5225834
    Abstract: A semiconductor integrated circuit having a test circuit built therein is disclosed which consists of an A/D converter to be connected to a peripheral circuit, a digital circuit connected to the A/D converter, a digital signal switching device for selectively connecting to the output of the A/D converter and that of the digital circuit, and a boundary scan output circuit connected to the output of the digital signal switching device, wherein the digital signal switching device connects the A/D converter to the boundary scan output circuit in a normal mode, while the signal fetched in the boundary scan output circuit is outputted therefrom in test mode. Semiconductor integrated circuits having an analog circuit built therein and an analog integrated circuit in which a test circuit is built-in are also disclosed.
    Type: Grant
    Filed: December 2, 1991
    Date of Patent: July 6, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Imai, Toshiaki Tsuji, Taku Takada, Seiichi Taguchi