Patents by Inventor Taku Umebayashi

Taku Umebayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11094729
    Abstract: A semiconductor device is provided as a back-illuminated solid-state imaging device. The device is manufactured by bonding a first semiconductor wafer with a pixel array in a half-finished product state and a second semiconductor wafer with a logic circuit in a half-finished product state together, making the first semiconductor wafer into a thin film, electrically connecting the pixel array and the logic circuit, making the pixel array and the logic circuit into a finished product state, and dividing the first semiconductor wafer and the second semiconductor being bonded together into microchips.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: August 17, 2021
    Inventors: Taku Umebayashi, Hiroshi Takahashi, Reijiroh Shohji
  • Patent number: 11043532
    Abstract: A semiconductor device according to an embodiment of the present technology, and the semiconductor device includes: a first substrate provided with a memory array; and a second substrate that is stacked with the first substrate, and is provided with a peripheral circuit that controls operation of the memory array.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: June 22, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Takashi Yokoyama, Taku Umebayashi
  • Publication number: 20210091133
    Abstract: A semiconductor device is provided as a back-illuminated solid-state imaging device. The device is manufactured by bonding a first semiconductor wafer with a pixel array in a half-finished product state and a second semiconductor wafer with a logic circuit in a half-finished product state together, making the first semiconductor wafer into a thin film, electrically connecting the pixel array and the logic circuit, making the pixel array and the logic circuit into a finished product state, and dividing the first semiconductor wafer and the second semiconductor being bonded together into microchips.
    Type: Application
    Filed: December 2, 2020
    Publication date: March 25, 2021
    Applicant: Sony Corporation
    Inventors: Taku Umebayashi, Hiroshi Takahashi, Reijiroh Shohji
  • Patent number: 10950647
    Abstract: A semiconductor device is provided as a back-illuminated solid-state imaging device. The device is manufactured by bonding a first semiconductor wafer with a pixel array in a half-finished product state and a second semiconductor wafer with a logic circuit in a half-finished product state together, making the first semiconductor wafer into a thin film, electrically connecting the pixel array and the logic circuit, making the pixel array and the logic circuit into a finished product state, and dividing the first semiconductor wafer and the second semiconductor being bonded together into microchips.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: March 16, 2021
    Assignee: SONY CORPORATION
    Inventors: Taku Umebayashi, Hiroshi Takahashi, Reijiroh Shohji
  • Publication number: 20210043676
    Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.
    Type: Application
    Filed: October 12, 2020
    Publication date: February 11, 2021
    Applicant: SONY CORPORATION
    Inventors: Taku UMEBAYASHI, Keiji TATANI, Hajime INOUE, Ryuichi KANAMURA
  • Patent number: 10916577
    Abstract: A semiconductor device is provided as a back-illuminated solid-state imaging device. The device is manufactured by bonding a first semiconductor wafer with a pixel array in a half-finished product state and a second semiconductor wafer with a logic circuit in a half-finished product state together, making the first semiconductor wafer into a thin film, electrically connecting the pixel array and the logic circuit, making the pixel array and the logic circuit into a finished product state, and dividing the first semiconductor wafer and the second semiconductor being bonded together into microchips.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: February 9, 2021
    Assignee: Sony Corporation
    Inventors: Taku Umebayashi, Hiroshi Takahashi, Reijiroh Shohji
  • Patent number: 10879299
    Abstract: A semiconductor device including a semiconductor substrate having a first surface and a second surface that face each other, and having an element region and an isolation region, the element region including a transistor in the first surface, and the isolation region including an element isolation layer surrounding the element region; and a contact plug extending from the first surface to the second surface in the isolation region of the semiconductor substrate.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: December 29, 2020
    Assignee: SONY CORPORATION
    Inventors: Takashi Yokoyama, Taku Umebayashi
  • Publication number: 20200365641
    Abstract: A semiconductor device having a first semiconductor section including a first wiring layer at one side thereof; a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other; a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication; and an opening, other than the opening for the conductive material, which extends through the first semiconductor section to the second wiring layer.
    Type: Application
    Filed: August 4, 2020
    Publication date: November 19, 2020
    Applicant: Sony Corporation
    Inventors: Hiroshi Takahashi, Taku Umebayashi
  • Patent number: 10840290
    Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: November 17, 2020
    Assignee: Sony Corporation
    Inventors: Taku Umebayashi, Keiji Tatani, Hajime Inoue, Ryuichi Kanamura
  • Publication number: 20200328244
    Abstract: A semiconductor device is provided as a back-illuminated solid-state imaging device. The device is manufactured by bonding a first semiconductor wafer with a pixel array in a half-finished product state and a second semiconductor wafer with a logic circuit in a half-finished product state together, making the first semiconductor wafer into a thin film, electrically connecting the pixel array and the logic circuit, making the pixel array and the logic circuit into a finished product state, and dividing the first semiconductor wafer and the second semiconductor being bonded together into microchips.
    Type: Application
    Filed: June 26, 2020
    Publication date: October 15, 2020
    Applicant: Sony Corporation
    Inventors: Taku Umebayashi, Hiroshi Takahashi, Reijiroh Shohji
  • Patent number: 10777600
    Abstract: A semiconductor device having a first semiconductor section including a first wiring layer at one side thereof; a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other; a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication; and an opening, other than the opening for the conductive material, which extends through the first semiconductor section to the second wiring layer.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: September 15, 2020
    Assignee: Sony Corporation
    Inventors: Hiroshi Takahashi, Taku Umebayashi
  • Publication number: 20200152685
    Abstract: A semiconductor device is provided as a back-illuminated solid-state imaging device. The device is manufactured by bonding a first semiconductor wafer with a pixel array in a half-finished product state and a second semiconductor wafer with a logic circuit in a half-finished product state together, making the first semiconductor wafer into a thin film, electrically connecting the pixel array and the logic circuit, making the pixel array and the logic circuit into a finished product state, and dividing the first semiconductor wafer and the second semiconductor being bonded together into microchips.
    Type: Application
    Filed: January 17, 2020
    Publication date: May 14, 2020
    Inventors: Taku Umebayashi, Hitoshi Takahashi, Reijiroh Shohji
  • Patent number: 10615334
    Abstract: The present disclosure relates to a memory cell structure, a method of manufacturing a memory, and a memory apparatus that are capable of providing a memory cell structure of an MRAM, which reduces resistance of drawn wiring to be connected to an MTJ, reduces an area of a memory cell, and avoids performance degradation of the MTJ due to heat. A memory cell includes: a transistor that uses a first diffusion layer formed in a bottom portion of a concave portion formed by processing a silicon substrate into a groove shape, and a second diffusion layer formed in upper end portions of two opposing sidewall portions of the concave portion, to form channels at portions between the first diffusion layer and the second diffusion layer in the two sidewall portions; and a memory element that is disposed below the first diffusion layer. The first diffusion layer is electrically connected to the memory element via a contact formed after the silicon substrate is thinned.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: April 7, 2020
    Assignee: SONY CORPORATION
    Inventors: Taku Umebayashi, Shunichi Sukegawa, Takashi Yokoyama, Masanori Hosomi, Yutaka Higo
  • Publication number: 20200035744
    Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.
    Type: Application
    Filed: August 29, 2019
    Publication date: January 30, 2020
    Applicant: SONY CORPORATION
    Inventors: Taku UMEBAYASHI, Keiji TATANI, Hajime INOUE, Ryuichi KANAMURA
  • Patent number: 10535700
    Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: January 14, 2020
    Assignee: Sony Corporation
    Inventors: Taku Umebayashi, Keiji Tatani, Hajime Inoue, Ryuichi Kanamura
  • Publication number: 20190378871
    Abstract: A semiconductor device having a first semiconductor section including a first wiring layer at one side thereof; a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other; a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication; and an opening, other than the opening for the conductive material, which extends through the first semiconductor section to the second wiring layer.
    Type: Application
    Filed: August 22, 2019
    Publication date: December 12, 2019
    Applicant: Sony Corporation
    Inventors: Hiroshi Takahashi, Taku Umebayashi
  • Publication number: 20190363129
    Abstract: A semiconductor device according to an embodiment of the present technology, and the semiconductor device includes: a first substrate provided with a memory array; and a second substrate that is stacked with the first substrate, and is provided with a peripheral circuit that controls operation of the memory array.
    Type: Application
    Filed: December 13, 2017
    Publication date: November 28, 2019
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takashi YOKOYAMA, Taku UMEBAYASHI
  • Publication number: 20190363130
    Abstract: A semiconductor device according to an embodiment of the present disclosure includes: a first substrate provided with an active element; and a second substrate laminated with the first substrate and electrically coupled to the first substrate, in which the second substrate is provided with a first transistor configuring a logic circuit on a first surface and with a non-volatile memory element on a second surface opposite to the first surface.
    Type: Application
    Filed: January 11, 2018
    Publication date: November 28, 2019
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takashi YOKOYAMA, Taku UMEBAYASHI, Nobutoshi FUJII
  • Patent number: 10475845
    Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: November 12, 2019
    Assignee: Sony Corporation
    Inventors: Taku Umebayashi, Keiji Tatani, Hajime Inoue, Ryuichi Kanamura
  • Patent number: 10438985
    Abstract: A semiconductor device having a first semiconductor section including a first wiring layer at one side thereof; a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other; a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication; and an opening, other than the opening for the conductive material, which extends through the first semiconductor section to the second wiring layer.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: October 8, 2019
    Assignee: Sony Corporation
    Inventors: Hiroshi Takahashi, Taku Umebayashi