Abstract: A synchronisation symbol detector that comprises two correlation modules and a comparison module. The first correlation module performs one or more correlations between the input signal and a down-converted version of the input signal and generates a first correlation metric from the one or more first correlations. The second correlation module performs one or more second correlations between the input signal and an up-converted version of the input signal and generates a second correlation metric from the one or more second correlations. The comparison module is configured to compare the first correlation metric and the second correlation metric and determine whether the input signal comprises a synchronisation symbol based on the comparison.

Abstract: A synchronisation symbol detector that comprises two correlation modules and a comparison module. The first correlation module performs one or more correlations between the input signal and a down-converted version of the input signal and generates a first correlation metric from the one or more first correlations. The second correlation module performs one or more second correlations between the input signal and an up-converted version of the input signal and generates a second correlation metric from the one or more second correlations. The comparison module is configured to compare the first correlation metric and the second correlation metric and determine whether the input signal comprises a synchronisation symbol based on the comparison.

Abstract: A synchronisation symbol detector that comprises two correlation modules and a comparison module. The first correlation module performs one or more correlations between the input signal and a down-converted version of the input signal and generates a first correlation metric from the one or more first correlations. The second correlation module performs one or more second correlations between the input signal and an up-converted version of the input signal and generates a second correlation metric from the one or more second correlations. The comparison module is configured to compare the first correlation metric and the second correlation metric and determine whether the input signal comprises a synchronisation symbol based on the comparison.

Abstract: A synchronisation symbol detector that comprises two correlation modules and a comparison module. The first correlation module performs one or more correlations between the input signal and a down-converted version of the input signal and generates a first correlation metric from the one or more first correlations. The second correlation module performs one or more second correlations between the input signal and an up-converted version of the input signal and generates a second correlation metric from the one or more second correlations. The comparison module is configured to compare the first correlation metric and the second correlation metric and determine whether the input signal comprises a synchronisation symbol based on the comparison.

Abstract: Efficient methods and apparatus for tracking decision-feedback equalizer (DFE) coefficients are described. In an embodiment, updated coefficients for a feed-forward equalizer (FFE) are generated using conventional methods and then these are used, along with an averaged updated value of channel impulse response (CIR) estimate to generate updated DFE coefficients. In an embodiment, the updated DFE coefficients are generated by multiplying the updated CIR estimate (in the frequency domain) and the updated FFE coefficients (also in the frequency domain). The resultant updated DFE coefficients in the frequency domain may then be converted into the time domain before outputting to the DFE.

Abstract: Efficient methods and apparatus for tracking decision-feedback equaliser (DFE) coefficients are described. In an embodiment, updated coefficients for a feed-forward equaliser (FFE) are generated using conventional methods and then these are used, along with an averaged updated value of channel impulse response (CIR) estimate to generate updated DFE coefficients. In an embodiment, the updated DFE coefficients are generated by multiplying the updated CIR estimate (in the frequency domain) and the updated FFE coefficients (also in the frequency domain). The resultant updated DFE coefficients in the frequency domain may then be converted into the time domain before outputting to the DFE.

Abstract: Efficient methods and apparatus for tracking decision-feedback equaliser (DFE) coefficients are described. In an embodiment, updated coefficients for a feed-forward equaliser (FFE) are generated using conventional methods and then these are used, along with an averaged updated value of channel impulse response (CIR) estimate to generate updated DFE coefficients. In an embodiment, the updated DFE coefficients are generated by multiplying the updated CIR estimate (in the frequency domain) and the updated FFE coefficients (also in the frequency domain). The resultant updated DFE coefficients in the frequency domain may then be converted into the time domain before outputting to the DFE.

Abstract: Methods of efficient calculation of initial equalizer coefficients are described. In a first stage, a channel matched filter is generated based on an estimate of CIR and then used to filter the CIR estimate. In a second stage, initial FFE coefficients are calculated from a portion of the match filtered CIR and then these initial FFE coefficients and the estimate of CIR may be used to generate initial DFE coefficients. In various embodiments, a window is applied to the CIR estimate before the matched filter is generated. In various embodiments, the second stage is iterated to minimize the pre-echoes following the FFE.

Abstract: Methods and circuits for controlling an automatic gain control (AGC) circuit wherein the AGC circuit is used to adjust the gain of a signal input to an analog to digital converter. The method includes obtaining a plurality of samples from the output of the analog to digital converter and determining whether the amplitude of each sample is greater than a threshold amplitude value. If the amplitude of a sample is greater than the threshold amplitude value then a counter value is incremented. The target average amplitude of the automatic gain control circuit is then periodically adjusted based on the counter value.

Abstract: Methods of efficient calculation of initial equaliser coefficients are described. In a first stage, a channel matched filter is generated based on an estimate of CIR and then used to filter the CIR estimate. In a second stage, initial FFE coefficients are calculated from a portion of the match filtered CIR and then these initial FFE coefficients and the estimate of CIR may be used to generate initial DFE coefficients. In various embodiments, a window is applied to the CIR estimate before the matched filter is generated. In various embodiments, the second stage is iterated to minimise the pre-echoes following the FFE.

Abstract: Efficient methods and apparatus for tracking decision-feedback equaliser (DFE) coefficients are described. In an embodiment, updated coefficients for a feed-forward equaliser (FFE) are generated using conventional methods and then these are used, along with an averaged updated value of channel impulse response (CIR) estimate to generate updated DFE coefficients. In an embodiment, the updated DFE coefficients are generated by multiplying the updated CIR estimate (in the frequency domain) and the updated FFE coefficients (also in the frequency domain). The resultant updated DFE coefficients in the frequency domain may then be converted into the time domain before outputting to the DFE.

Abstract: Methods and circuits for controlling an automatic gain control (AGC) circuit wherein the AGC circuit is used to adjust the gain of a signal input to an analog to digital converter. The method includes obtaining a plurality of samples from the output of the analog to digital converter and determining whether the amplitude of each sample is greater than a threshold amplitude value. If the amplitude of a sample is greater than the threshold amplitude value then a counter value is incremented. The target average amplitude of the automatic gain control circuit is then periodically adjusted based on the counter value.

Abstract: An orthogonal frequency division multiplexed (OFDM) demodulation device for demodulating an OFDM signal is disclosed. The device includes a means that demodulates the OFDM signal to produce a baseband OFDM signal. The device also includes a means that detects a carrier frequency offset amount that is a shift amount of a center frequency of the baseband OFDM signal, based on correlation of subcarriers to which a predetermined signal is inserted. Additionally, the device includes a means that controls a frequency of the carrier signal depending on the carrier frequency offset amount. The means that detects the carrier frequency offset amount divides subcarriers into a plurality of groups, calculates a correlation value with respect to an adjacent transmission symbol for each of the groups, adds the correlation values to each other for all the groups, and defines an offset amount assumed when a maximum addition-result value is obtained as the carrier frequency offset amount.

Abstract: A demodulator includes a complex conjugate signal generator to generate a complex conjugate signal of an OFDM time domain signal (complex signal including an I channel signal and Q channel signal) supplied from an orthogonal demodulation circuit, a delaying unit to delay, by an integral multiple of a predetermined period 1H or 2H, the complex conjugate signal supplied from the complex conjugate signal generator, a complex multiplier to make complex multiplication on the basis of the complex signal generated by the orthogonal demodulation circuit and complex conjugate signal delayed by the integral multiple of the predetermined period by the delay unit, and a determining unit to determine whether an interference wave is included in the modulated signal by making a comparison between the complex multiplication value resulted from the complex multiplication made by the complex multiplier and an arbitrary threshold.

Abstract: An orthogonal frequency division multiplexing (OFDM) demodulating apparatus includes a delay profile creating section, a Fourier converting section, a pilot signal extracting section, a transmission path characteristic estimating section, an inverse Fourier converting section, and a window control section. In this case, the window control section creates a delay profile for defining a calculation range by leaving a path which exists at a same position in both the delay profiles created by the delay profile creating section and the inverse Fourier converting section and the number of times of detection which is equal to or higher than a threshold value and defines a higher threshold value for the path at a predetermined position from the position of the main path within the delay profile created by the inverse Fourier converting section than for the paths at the other positions.

Abstract: The present invention provides an OFDM demodulation device for demodulating an orthogonal frequency division multiplexed (OFDM) signal whose transmission unit is a transmission symbol produced by quadrature modulation in such a way that information is divided for a plurality of subcarriers in a predetermined band. The OFDM demodulation device includes a carrier frequency offset detecting circuit (20).

Abstract: A receiver for recovering data from a received symbol of signal samples generated in accordance with Orthogonal Frequency Division Multiplexing (OFDM), the OFDM symbol including pilot carrier signals, the receiver including a pilot assisted channel estimator comprising a pilot extractor configured to extract the pilot carrier signals from the signal samples, and to generate an estimate of a sample of a channel frequency response for each of the pilot carrier signals in the received OFDM symbol, by comparing the extracted pilot carrier signals with predetermined versions of the pilot carrier signals, and a frequency interpolation filter configured to interpolate the samples of the channel frequency response estimate, and a filter controller, the frequency response of the frequency interpolation filter including a pass bandwidth which is adjustable, and the filter controller configured to adjust the bandwidth of the frequency interpolation filter to reduce noise in the estimate of channel frequency response.

Abstract: A demodulator includes a complex conjugate signal generator to generate a complex conjugate signal of an OFDM time domain signal (complex signal including an I channel signal and Q channel signal) supplied from an orthogonal demodulation circuit, a delaying unit to delay, by an integral multiple of a predetermined period 1H or 2H, the complex conjugate signal supplied from the complex conjugate signal generator, a complex multiplier to make complex multiplication on the basis of the complex signal generated by the orthogonal demodulation circuit and complex conjugate signal delayed by the integral multiple of the predetermined period by the delay unit, and a determining unit to determine whether an interference wave is included in the modulated signal by making a comparison between the complex multiplication value resulted from the complex multiplication made by the complex multiplier and an arbitrary threshold.

Abstract: A receiver for recovering data from a received symbol of signal samples generated in accordance with Orthogonal Frequency Division Multiplexing (OFDM) includes a pilot assisted channel estimator operable to generate an estimate of a transmission channel through which the received OFDM symbol has passed. The OFDM symbol includes pilot signals provided at different sub-carrier locations for each of a set of OFDM symbols, the sub-carrier locations of the pilot signals being repeated for subsequent sets of symbols. The pilot assisted channel estimator includes a pilot extractor, a time interpolation filter controller and an adaptive bandwidth interpolation filter.

Abstract: An orthogonal frequency division multiplexing (OFDM) demodulating apparatus includes a delay profile creating section, a Fourier converting section, a pilot signal extracting section, a transmission path characteristic estimating section, an inverse Fourier converting section, and a window control section. In this case, the window control section creates a delay profile for defining a calculation range by leaving a path which exists at a same position in both the delay profiles created by the delay profile creating section and the inverse Fourier converting section and the number of times of detection which is equal to or higher than a threshold value and defines a higher threshold value for the path at a predetermined position from the position of the main path within the delay profile created by the inverse Fourier converting section than for the paths at the other positions.