Abstract: Provided is a vehicle control system for avoiding a collection between a right-turning vehicle and a straight-through vehicle without decreasing comfort for an occupant. In the system, a first vehicle V1 and a second vehicle V2 retain high-precision map data for identifying a traveling lane. When the first vehicle V1 traveling in an autonomous driving mode intends to turn right from a right turn lane at an intersection ahead based on the high-precision map data, the first vehicle V1 transmits a right turn notification indicating the intention to turn right to nearby vehicles using vehicle-to-vehicle communications. When the second vehicle V2 traveling in an autonomous driving mode intends to travel straight at an intersection ahead, the second vehicle V2 recognizes a right-turning vehicle in an oncoming lane at the intersection upon receiving the right turn notification from the right-turning vehicle, and performs a predetermined control for collision avoidance.

Abstract: A vehicle system includes: a map processing unit that creates local map data based on high accuracy map data and a position of an own vehicle; and an autonomous driving control unit that creates a travel plan for autonomous traveling of the own vehicle based on the local map data and controls traveling of the own vehicle according to the travel plan. The map processing unit creates multiple pieces of transmission data by dividing the local map data so as to correspond to regions on a map and transmits the multiple pieces of transmission data to the autonomous driving control unit. The map processing unit changes a shape and a size of the region on the map corresponding to each piece of transmission data based on selection information which decides a travel mode.

Abstract: A data compression method is used for compressing data indicating a gradient of a route. The data compression method includes: acquiring a gradient table that shows gradient values in respective sections arranged between a starting point of the route and an ending point thereof, the sections including one section and an adjacent section adjacent to the one section: ranking the gradient values; and in a case where the gradient value of the one section and the gradient value of the adjacent section are in a same rank, integrating the gradient value of the one section and the gradient value of the adjacent section and generating a compressed gradient table that shows a distance and a corresponding rank of the section having the same rank.

Abstract: The semiconductor integrated circuit device includes a T-type switch circuit TS[k] that is between an input port A[k] and an input terminal Ain of an analog/digital conversion circuit and that includes first, second, and third PMOS transistors MP1, MP2, and MPc, and first, second, and third NMOS transistors MN1, MN2, and MNc; and a fourth PMOS transistor MPu for pre-charging the input terminal Ain to a power supply voltage VCCA. In detecting the presence or absence of a disconnection from the input port A[k] to a signal input terminal Vint[k], first, the input terminal Ain is pre-charged to the power supply voltage VCCA via the fourth PMOS transistor MPu and also the second NMOS transistor MN2 and the second PMOS transistor MP2 are turned on, and the first NMOS transistor MN1, the first PMOS transistor MP1, the third PMOS transistor MPc, and third the NMOS transistor MNc are turned off.

Abstract: The semiconductor integrated circuit device includes a T-type switch circuit TS[k] that is between an input port A[k] and an input terminal Ain of an analog/digital conversion circuit and that includes first, second, and third PMOS transistors MP1, MP2, and MPc, and first, second, and third NMOS transistors MN1, MN2, and MNc; and a fourth PMOS transistor MPu for pre-charging the input terminal Ain to a power supply voltage VCCA. In detecting the presence or absence of a disconnection from the input port A[k] to a signal input terminal Vint[k], first, the input terminal Ain is pre-charged to the power supply voltage VCCA via the fourth PMOS transistor MPu and also the second NMOS transistor MN2 and the second PMOS transistor MP2 are turned on, and the first NMOS transistor MN1, the first PMOS transistor MP1, the third PMOS transistor MPc, and third the NMOS transistor MNc are turned off.

Abstract: The semiconductor integrated circuit device includes a T-type switch circuit TS[k] that is between an input port A[k] and an input terminal Ain of an analog/digital conversion circuit and that includes first, second, and third PMOS transistors MP1, MP2, and MPc, and first, second, and third NMOS transistors MN1, MN2, and MNc; and a fourth PMOS transistor MPu for pre-charging the input terminal Ain to a power supply voltage VCCA. In detecting the presence or absence of a disconnection from the input port A[k] to a signal input terminal Vint[k], first, the input terminal Ain is pre-charged to the power supply voltage VCCA via the fourth PMOS transistor MPu and also the second NMOS transistor MN2 and the second PMOS transistor MP2 are turned on, and the first NMOS transistor MN1, the first PMOS transistor MP1, the third PMOS transistor MPc, and third the NMOS transistor MNc are turned off.

Abstract: The semiconductor integrated circuit device includes a T-type switch circuit TS[k] that is between an input port A[k] and an input terminal Ain of an analog/digital conversion circuit and that includes first, second, and third PMOS transistors MP1, MP2, and MPc, and first, second, and third NMOS transistors MN1, MN2, and MNc; and a fourth PMOS transistor MPu for pre-charging the input terminal Ain to a power supply voltage VCCA. In detecting the presence or absence of a disconnection from the input port A[k] to a signal input terminal Vint[k], first, the input terminal Ain is pre-charged to the power supply voltage VCCA via the fourth PMOS transistor MPu and also the second NMOS transistor MN2 and the second PMOS transistor MP2 are turned on, and the first NMOS transistor MN1, the first PMOS transistor MP1, the third PMOS transistor MPc, and third the NMOS transistor MNc are turned off.

Abstract: The semiconductor integrated circuit device includes a T-type switch circuit TS[k] that is between an input port A[k] and an input terminal Ain of an analog/digital conversion circuit and that includes first, second, and third PMOS transistors MP1, MP2, and MPc, and first, second, and third NMOS transistors MN1, MN2, and MNc; and a fourth PMOS transistor MPu for pre-charging the input terminal Ain to a power supply voltage VCCA. In detecting the presence or absence of a disconnection from the input port A[k] to a signal input terminal Vint[k], first, the input terminal Ain is pre-charged to the power supply voltage VCCA via the fourth PMOS transistor MPu and also the second NMOS transistor MN2 and the second PMOS transistor MP2 are turned on, and the first NMOS transistor MN1, the first PMOS transistor MP1, the third PMOS transistor MPc, and third the NMOS transistor MNc are turned off.

Abstract: In a semiconductor integrated circuit, having a central processing unit, a clock generating unit, an A/D converter and a sample and hold signal generating circuit, noise from an element that operates in accordance with operation timing that is difficult to predict beforehand is reduced. In a calibration operation, in response to a clock signal from the clock generating unit, a sample and hold signal generating circuit supplies a plurality of clock signals sequentially to a sample and hold circuit of the A/D converter. By analyzing a plurality of digital signals that are sequentially output from an A/D conversion circuit of the A/D converter, a timing of a holding period for allowing A/D conversion under a low noise condition is selected from the clock signals. In normal operation, a clock signal selected by the calibration operation is supplied as a sample and hold control signal to the sample and hold circuit.

Abstract: A high-precision A/D conversion is realized while the number of external terminals used for an A/D converter is reduced. At the time of sampling, first to fifth switches are turned on and a sixth switch is turned off. Since a first resistor is set to a resistance value optimum for sampling, an impedance in the direction from a node A to the left side and an impedance in the direction from a node B to the left side almost match, and a large noise-cancelling effect is obtained. At the time of successive approximation, the first, second, third, and fifth switches are turned off and the fourth and sixth switches are turned on. Since a second resistor is set to a resistance value optimum for the successive approximation, the impedance in the direction from the node A to the left side and the impedance in the direction from the node B to the left side almost match, and a large noise-cancelling effect is obtained also at the time of successive approximation.

Abstract: The semiconductor integrated circuit device includes a T-type switch circuit TS[k] that is between an input port A[k] and an input terminal Ain of an analog/digital conversion circuit and that includes first, second, and third PMOS transistors MP1, MP2, and MPc, and first, second, and third NMOS transistors MN1, MN2, and MNc; and a fourth PMOS transistor MPu for pre-charging the input terminal Ain to a power supply voltage VCCA. In detecting the presence or absence of a disconnection from the input port A[k] to a signal input terminal Vint[k], first, the input terminal Ain is pre-charged to the power supply voltage VCCA via the fourth PMOS transistor MPu and also the second NMOS transistor MN2 and the second PMOS transistor MP2 are turned on, and the first NMOS transistor MN1, the first PMOS transistor MP1, the third PMOS transistor MPc, and third the NMOS transistor MNc are turned off.

Abstract: In a semiconductor integrated circuit, having a central processing unit, a clock generating unit, an A/D converter and a sample and hold signal generating circuit, noise from an element that operates in accordance with operation timing that is difficult to predict beforehand is reduced. In a calibration operation, in response to a clock signal from the clock generating unit, a sample and hold signal generating circuit supplies a plurality of clock signals sequentially to a sample and hold circuit of the A/D converter. By analyzing a plurality of digital signals that are sequentially output from an A/D conversion circuit of the A/D converter, a timing of a holding period for allowing A/D conversion under a low noise condition is selected from the clock signals. In normal operation, a clock signal selected by the calibration operation is supplied as a sample and hold control signal to the sample and hold circuit.

Abstract: A high-precision A/D conversion is realized while the number of external terminals used for an A/D converter is reduced. At the time of sampling, first to fifth switches are turned on and a sixth switch is turned off. Since a first resistor is set to a resistance value optimum for sampling, an impedance in the direction from a node A to the left side and an impedance in the direction from a node B to the left side almost match, and a large noise-cancelling effect is obtained. At the time of successive approximation, the first, second, third, and fifth switches are turned off and the fourth and sixth switches are turned on. Since a second resistor is set to a resistance value optimum for the successive approximation, the impedance in the direction from the node A to the left side and the impedance in the direction from the node B to the left side almost match, and a large noise-cancelling effect is obtained also at the time of successive approximation.