Patents by Inventor Takuji Ide
Takuji Ide has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10163740Abstract: A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.Type: GrantFiled: October 17, 2017Date of Patent: December 25, 2018Assignee: Renesas Electronics CorporationInventors: Bunji Yasumura, Fumio Tsuchiya, Hisanori Ito, Takuji Ide, Naoki Kawanabe, Masanao Sato
-
Publication number: 20180040521Abstract: A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.Type: ApplicationFiled: October 17, 2017Publication date: February 8, 2018Inventors: Bunji YASUMURA, Fumio TSUCHIYA, Hisanori ITO, Takuji IDE, Naoki KAWANABE, Masanao SATO
-
Patent number: 9824944Abstract: A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.Type: GrantFiled: September 29, 2016Date of Patent: November 21, 2017Assignee: Renesas Electronics CorporationInventors: Bunji Yasumura, Fumio Tsuchiya, Hisanori Ito, Takuji Ide, Naoki Kawanabe, Masanao Sato
-
Publication number: 20170018470Abstract: A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.Type: ApplicationFiled: September 29, 2016Publication date: January 19, 2017Inventors: Bunji YASUMURA, Fumio TSUCHIYA, Hisanori ITO, Takuji IDE, Naoki KAWANABE, Masanao SATO
-
Publication number: 20150137125Abstract: A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.Type: ApplicationFiled: January 5, 2015Publication date: May 21, 2015Inventors: Bunji Yasumura, Fumio Tsuchiya, Hisanori Ito, Takuji Ide, Naoki Kawanabe, Masanao Sato
-
Patent number: 8946705Abstract: A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.Type: GrantFiled: May 12, 2010Date of Patent: February 3, 2015Assignee: Renesas Electronics CorporationInventors: Bunji Yasumura, Fumio Tsuchiya, Hisanori Ito, Takuji Ide, Naoki Kawanabe, Masanao Sato
-
Publication number: 20100295043Abstract: A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.Type: ApplicationFiled: May 12, 2010Publication date: November 25, 2010Inventors: Bunji YASUMURA, Fumio Tsuchiya, Hisanori Ito, Takuji Ide, Naoki Kawanabe, Masanao Sato
-
Patent number: 7199469Abstract: The cost of a semiconductor device is to be reduced. An electrical connection between a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip is made through an inner lead portion of a lead disposed at a position around the first semiconductor chip and two bonding wires.Type: GrantFiled: September 28, 2001Date of Patent: April 3, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Toru Ishida, Tetsuharu Urawa, Fujio Ito, Tomoo Matsuzawa, Kazunari Suzuki, Akihiko Kameoka, Hiromichi Suzuki, Takuji Ide
-
Patent number: 6879037Abstract: A semiconductor device according to the invention is provided with square first semiconductor chip and second semiconductor chip laminated with each one main surface opposite, a supporting lead a part of which is arranged between one main surface of the first semiconductor chip and one main surface of the second semiconductor chip and a resin sealing body that seals the first semiconductor chip, the second semiconductor chip and the supporting lead and is characterized in that the respective one main surfaces of the first semiconductor chip and the second semiconductor chip are bonded to a part of the supporting lead via an adhesive layer and a part of the supporting lead is formed so that it has smaller width than the respective sides of the first semiconductor chip and the second semiconductor chip.Type: GrantFiled: August 27, 2003Date of Patent: April 12, 2005Assignee: Renesas Technology Corp.Inventors: Takashi Wada, Takuji Ide, Eiji Niihara, Shunichiro Fujioka, Mitsue Ueno
-
Patent number: 6727114Abstract: A semiconductor device according to the invention is provided with square first semiconductor chip and second semiconductor chip laminated with each one main surface opposite, a supporting lead a part of which is arranged between one main surface of the first semiconductor chip and one main surface of the second semiconductor chip and a resin sealing body that seals the first semiconductor chip, the second semiconductor chip and the supporting lead and is characterized in that the respective one main surfaces of the first semiconductor chip and the second semiconductor chip are bonded to a part of the supporting lead via an adhesive layer and a part of the supporting lead is formed so that it has smaller width than the respective sides of the first semiconductor chip and the second semiconductor chip.Type: GrantFiled: March 20, 2001Date of Patent: April 27, 2004Assignee: Hitachi, Ltd.Inventors: Takashi Wada, Takuji Ide, Eiji Niihara, Shunichiro Fujioka, Mitsue Ueno
-
Publication number: 20040056363Abstract: A semiconductor device according to the invention is provided with square first semiconductor chip and second semiconductor chip laminated with each one main surface opposite, a supporting lead a part of which is arranged between one main surface of the first semiconductor chip and one main surface of the second semiconductor chip and a resin sealing body that seals the first semiconductor chip, the second semiconductor chip and the supporting lead and is characterized in that the respective one main surfaces of the first semiconductor chip and the second semiconductor chip are bonded to a part of the supporting lead via an adhesive layer and a part of the supporting lead is formed so that it has smaller width than the respective sides of the first semiconductor chip and the second semiconductor chip.Type: ApplicationFiled: August 27, 2003Publication date: March 25, 2004Applicant: Hitachi, Ltd.Inventors: Takashi Wada, Takuji Ide, Eiji Niihara, Shunichiro Fujioka, Mitsue Ueno
-
Patent number: 6420783Abstract: A semiconductor device according to the invention is provided with square first semiconductor chip and second semiconductor chip laminated with each one main surface opposite, a supporting lead a part of which is arranged between one main surface of the first semiconductor chip and one main surface of the second semiconductor chip and a resin sealing body that seals the first semiconductor chip, the second semiconductor chip and the supporting lead and is characterized in that the respective one main surfaces of the first semiconductor chip and the second semiconductor chip are bonded to a part of the supporting lead via an adhesive layer and a part of the supporting lead is formed so that it has smaller width than the respective sides of the first semiconductor chip and the second semiconductor chip.Type: GrantFiled: March 7, 2001Date of Patent: July 16, 2002Assignee: Hitachi, Ltd.Inventors: Takashi Wada, Takuji Ide, Eiji Niihara, Shunichiro Fujioka, Mitsue Ueno
-
Publication number: 20020043717Abstract: The cost of a semiconductor device is to be reduced. An electrical connection between a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip is made through an inner lead portion of a lead disposed at a position around the first semiconductor chip and two bonding wires.Type: ApplicationFiled: September 28, 2001Publication date: April 18, 2002Inventors: Toru Ishida, Tetsuharu Urawa, Fujio Ito, Tomoo Matsuzawa, Kazunari Suzuki, Akihiko Kameoka, Hiromichi Suzuki, Takuji Ide
-
Publication number: 20020027266Abstract: A semiconductor device according to the invention is provided with square first semiconductor chip and second semiconductor chip laminated with each one main surface opposite, a supporting lead a part of which is arranged between one main surface of the first semiconductor chip and one main surface of the second semiconductor chip and a resin sealing body that seals the first semiconductor chip, the second semiconductor chip and the supporting lead and is characterized in that the respective one main surfaces of the first semiconductor chip and the second semiconductor chip are bonded to a part of the supporting lead via an adhesive layer and a part of the supporting lead is formed so that it has smaller width than the respective sides of the first semiconductor chip and the second semiconductor chip.Type: ApplicationFiled: March 20, 2001Publication date: March 7, 2002Inventors: Takashi Wada, Takuji Ide, Eiji Niihara, Shunichiro Fujioka, Mitsue Ueno
-
Publication number: 20010028107Abstract: A semiconductor device according to the invention is provided with square first semiconductor chip and second semiconductor chip laminated with each one main surface opposite, a supporting lead a part of which is arranged between one main surface of the first semiconductor chip and one main surface of the second semiconductor chip and a resin sealing body that seals the first semiconductor chip, the second semiconductor chip and the supporting lead and is characterized in that the respective one main surfaces of the first semiconductor chip and the second semiconductor chip are bonded to a part of the supporting lead via an adhesive layer and a part of the supporting lead is formed so that it has smaller width than the respective sides of the first semiconductor chip and the second semiconductor chip.Type: ApplicationFiled: March 7, 2001Publication date: October 11, 2001Inventors: Takashi Wada, Takuji Ide, Eiji Niihara, Shunichiro Fujioka, Mitsue Ueno