Patents by Inventor Takuji Maekawa
Takuji Maekawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240413208Abstract: A molding is formed by laminating an aggregate of SiC and a paste containing Si and C powders on an epitaxial layer of SiC formed on a support substrate of SiC to form an intermediate sintered body in which polycrystalline SiC is produced from the Si and C powders by reaction sintering, free Si is carbonized to SiC to form a sintered body layer, and the support substrate is removed from the epitaxial layer to form a semiconductor substrate in which the epitaxial layer and the sintered body layer are laminated.Type: ApplicationFiled: August 19, 2024Publication date: December 12, 2024Applicant: ROHM CO., LTD.Inventors: Takuji MAEKAWA, Keiju SATO
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Publication number: 20240332081Abstract: Provided is a method for manufacturing a semiconductor substrate, including: a step of forming a graphene layer on a Si surface of a SiC single crystal substrate; a step of forming a SiC-epitaxial growth layer on the graphene layer; a step of forming a stress layer on the SiC-epitaxial growth layer; a step of attaching a graphite substrate on the stress layer; a step of detaching the graphene layer and the SiC-epitaxial growth layer; a step of forming a SiC polycrystalline growth layer on a C surface of the SiC-epitaxial growth layer from which the graphene layer is detached; and a step of removing the graphite substrate, in which the stress layer generates a stress that facilitates detachment between the graphene layer and the SiC-epitaxial growth layer.Type: ApplicationFiled: March 29, 2024Publication date: October 3, 2024Applicant: ROHM CO., LTD.Inventors: Makoto TAKAMURA, Takuji MAEKAWA, Mitsuru MORIMOTO
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Publication number: 20240328032Abstract: The present disclosure provides a support tool, for a temporary substrate using a support plate. The support tool includes: a first dummy substrate and a second dummy substrate; and a support, supporting the first dummy substrate and the second dummy substrate, and including at least three of the support plates. The support plate is fitted with the first dummy substrate through a first groove of the plurality of grooves, and fitted with the second dummy substrate through a second groove of the plurality of grooves. The support is configured to support the temporary substrate inserted into a third groove of the plurality of grooves of the support plate excluding the first groove and the second groove.Type: ApplicationFiled: March 22, 2024Publication date: October 3, 2024Applicant: ROHM CO., LTD.Inventors: Makoto TAKAMURA, Mitsuru MORIMOTO, Takuji MAEKAWA
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Publication number: 20240321970Abstract: A semiconductor substrate includes a drift layer of a first layer formed of a single crystal SiC semiconductor and a buffer layer and a substrate layer of a second layer that is formed of a SiC semiconductor which includes a polycrystalline structure and is formed on the surface of the first layer, in which the second layer (12) is formed on the surface of the drift layer of the first layer by means of CVD growth, the drift layer of the first layer is formed by means of epitaxial growth, and accordingly, defects occurring at a junction interface of the semiconductor substrate including the single crystal SiC layer and the polycrystal SiC layer are suppressed, and manufacturing costs are also reduced.Type: ApplicationFiled: June 5, 2024Publication date: September 26, 2024Inventors: Takuji MAEKAWA, Mitsuru MORIMOTO
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Patent number: 12074201Abstract: A semiconductor substrate includes a drift layer of a first layer formed of a single crystal SiC semiconductor and a buffer layer and a substrate layer of a second layer that is formed of a SiC semiconductor which includes a polycrystalline structure and is formed on the surface of the first layer, in which the second layer (12) is formed on the surface of the drift layer of the first layer by means of CVD growth, the drift layer of the first layer is formed by means of epitaxial growth, and accordingly, defects occurring at a junction interface of the semiconductor substrate including the single crystal SiC layer and the polycrystal SiC layer are suppressed, and manufacturing costs are also reduced.Type: GrantFiled: January 31, 2022Date of Patent: August 27, 2024Assignee: ROHM CO., LTD.Inventors: Takuji Maekawa, Mitsuru Morimoto
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Patent number: 12040363Abstract: A semiconductor substrate includes a drift layer of a first layer formed of a single crystal SiC semiconductor and a buffer layer and a substrate layer of a second layer that is formed of a SiC semiconductor which includes a polycrystalline structure and is formed on the surface of the first layer, in which the second layer (12) is formed on the surface of the drift layer of the first layer by means of CVD growth, the drift layer of the first layer is formed by means of epitaxial growth, and accordingly, defects occurring at a junction interface of the semiconductor substrate including the single crystal SiC layer and the polycrystal SiC layer are suppressed, and manufacturing costs are also reduced.Type: GrantFiled: January 31, 2022Date of Patent: July 16, 2024Assignee: ROHM CO., LTD.Inventors: Takuji Maekawa, Mitsuru Morimoto
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Publication number: 20240153763Abstract: Systems and methods for growth of silicon carbide over a layer comprising graphene and/or hexagonal boron nitride, and related articles, are generally described. In some embodiments, a SiC film is fabricated over a layer comprising graphene and/or hexagonal boron nitride, which in turn is disposed over a substrate. The layer and/or the substrate may be lattice-matched with the SiC film to reduce defect density in the SiC film. The fabricated SiC film may then be removed from the substrate via, for example, a stressor attached to the SiC film. In certain cases, the layer serves as a reusable platform for growing SiC films and also serves a release layer that allows fast, precise, and repeatable release at the layer surface.Type: ApplicationFiled: October 13, 2023Publication date: May 9, 2024Applicants: Massachusetts Institute of Technology, The Government of the United States of America, as Represented by the Secretary of the Navy, ROHM Co. Ltd.Inventors: Rachael L. Myers-Ward, Jeehwan Kim, Kuan Qiao, Wei Kong, David Kurt Gaskill, Takuji Maekawa, Noriyuki Masago
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Publication number: 20230374698Abstract: A fabricating apparatus (2) of an sic epitaxial wafer disclosed herein includes: a growth furnace (100A); a gas mixing preliminary chamber (107) disposed outside the growth furnace and configured to mix carrier gas and/or material gas and to regulate a pressure thereof; a wafer boat (210) configured so that a plurality of SiC wafer pairs (200WP), in which two substrates each having an SiC single crystal in contact with each other in a back-to-back manner, are disposed at equal intervals with a gap therebetween; and a heating unit (101) configured to heat the wafer boat disposed in the growth furnace to an epitaxial growth temperature. The carrier gas and/or the material gas are introduced into the growth furnace after preliminarily being mixed and pressure-regulated in the gas mixing preliminary chamber (107) to grow an SiC layer on a surface of each of the plurality of SiC wafer pairs.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Applicant: ROHM CO., LTD.Inventors: Makoto TAKAMURA, Takuji MAEKAWA, Mitsuru MORIMOTO, Noriyuki MASAGO, Takayasu OKA
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Publication number: 20230369400Abstract: A semiconductor substrate (1) according to an embodiment includes: a hexagonal SiC single crystal layer (13I); an SiC epitaxial growth layer (12E) disposed on an Si plane of an SiC single crystal layer (13I); and an SiC polycrystalline growth layer (18PC) disposed on a C plane opposite to the Si plane of the SiC single crystal layer (13I). The SiC single crystal layer (13I) includes a single crystal SiC thin layer (10HE) obtained by weakening the hydrogen ion implantation layer (10HI), and a phosphorus ion implantation layer (10PI). The phosphorus ion implantation layer (10PI) is disposed between the single crystal SiC thin layer (10HE) and the SiC polycrystalline growth layer (18PC). Consequently, the present disclosure provides a low-cost and high-quality semiconductor substrate and a fabrication method thereof.Type: ApplicationFiled: July 21, 2023Publication date: November 16, 2023Applicant: ROHM CO., LTD.Inventors: Makoto TAKAMURA, Takuji MAEKAWA, Mitsuru MORIMOTO, Noriyuki MASAGO, Takayasu OKA
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Publication number: 20230369412Abstract: A semiconductor substrate (1) disclosed herein includes: an SiC single crystal substrate (10SB); a graphene layer (11GR) disposed on an Si plane of the SiC single crystal substrate (10SB); an SiC epitaxial growth layer (12RE) disposed above the SiC single crystal substrate (10SB) via the graphene layer (11GR); and a polycrystalline Si layer (15PS) disposed on an Si plane of the SiC epitaxial growth layer (12RE). The semiconductor substrate may include a graphite substrate or an silicon substrate disposed on a polycrystalline Si layer (15PS). The semiconductor substrate may further include an SiC polycrystalline growth layer (18PC) disposed on a C plane of the SiC epitaxial growth layer (12RE). Consequently, the present disclosure provides a low-cost and high-quality semiconductor substrate and a fabrication method thereof.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Applicant: ROHM CO., LTD.Inventors: Makoto TAKAMURA, Takuji MAEKAWA, Mitsuru MORIMOTO, Noriyuki MASAGO, Takayasu OKA
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Publication number: 20230317450Abstract: A semiconductor substrate (1) includes: an SiC single crystal substrate (10SB), a first graphene layer (11GR1) disposed on an Si plane of the SiC single crystal substrate 10SB; an SiC epitaxial growth layer (12RE) formed above the SiC single crystal substrate via the first graphene layer; and a second graphene layer (11GR2) disposed on an Si plane of the SiC epitaxial growth layer. There is also included an SiC polycrystalline substrate (16P) provisionally bonded onto the SiC epitaxial growth layer via the second graphene layer. The SiC single crystal substrate is able to be reused by being separated from the SiC epitaxial growth layer. This semiconductor substrate further includes an SiC polycrystalline growth layer (18PC) CVD grown on the C plane of the SiC epitaxial growth layer; and the SiC epitaxial growth layer is transferred to the SiC polycrystalline growth layer.Type: ApplicationFiled: June 7, 2023Publication date: October 5, 2023Applicant: ROHM CO., LTD.Inventors: Noriyuki MASAGO, Takuji MAEKAWA, Mitsuru MORIMOTO, Takayasu OKA
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Publication number: 20220157943Abstract: A semiconductor substrate includes a drift layer of a first layer formed of a single crystal SiC semiconductor and a buffer layer and a substrate layer of a second layer that is formed of a SiC semiconductor which includes a polycrystalline structure and is formed on the surface of the first layer, in which the second layer (12) is formed on the surface of the drift layer of the first layer by means of CVD growth, the drift layer of the first layer is formed by means of epitaxial growth, and accordingly, defects occurring at a junction interface of the semiconductor substrate including the single crystal SiC layer and the polycrystal SiC layer are suppressed, and manufacturing costs are also reduced.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Inventors: Takuji MAEKAWA, Mitsuru MORIMOTO
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Patent number: 11004938Abstract: A semiconductor substrate structure includes: a substrate; and an epitaxial growth layer bonded to the substrate, wherein the substrate and the epitaxial growth layer are bonded by a room-temperature bonding or a diffusion bonding.Type: GrantFiled: May 29, 2019Date of Patent: May 11, 2021Assignee: ROHM CO., LTD.Inventors: Takuji Maekawa, Mitsuru Morimoto, Makoto Takamura
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Publication number: 20210125826Abstract: Systems and methods for growth of silicon carbide over a layer comprising graphene and/or hexagonal boron nitride, and related articles, are generally described. In some embodiments, a SiC film is fabricated over a layer comprising graphene and/or hexagonal boron nitride, which in turn is disposed over a substrate. The layer and/or the substrate may be lattice-matched with the SiC film to reduce defect density in the SiC film. The fabricated SiC film may then be removed from the substrate via, for example, a stressor attached to the SiC film. In certain cases, the layer serves as a reusable platform for growing SiC films and also serves a release layer that allows fast, precise, and repeatable release at the layer surface.Type: ApplicationFiled: June 21, 2019Publication date: April 29, 2021Applicants: Massachusetts Institute of Technology, The Government of the United States of America, as Represented by the Secretary of the Navy, ROHM Co., Ltd.Inventors: Rachael L. Myers-Ward, Jeehwan Kim, Kuan Qiao, Wei Kong, David Kurt Gaskill, Takuji Maekawa, Noriyuki Masago
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Publication number: 20190371894Abstract: A semiconductor substrate structure includes: a substrate; and an epitaxial growth layer bonded to the substrate, wherein the substrate and the epitaxial growth layer are bonded by a room-temperature bonding or a diffusion bondingType: ApplicationFiled: May 29, 2019Publication date: December 5, 2019Inventors: Takuji MAEKAWA, Mitsuru MORIMOTO, Makoto TAKAMURA
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Patent number: 10184894Abstract: A target is irradiated in a time-shared manner with a visible-light-range illumination light source and an infrared laser beam for Raman scattering, and a target image is formed with an image-capturing lens on a CIGS image sensor provided with a visible-light-range filter, a narrow-band infrared filter for Raman-scattered light measurement, and a near-band reference narrow-band infrared filter that does not let Raman-scattered light pass through. In a preliminary measurement, a plurality of normal sections are measured and averaged, and by using the same as a reference, an actual measurement of Raman scattering is performed. In displaying a visible-light image with the CIGS image sensor, superimposed display is performed to specify sections where Raman scattering is detected, and superimposed display positions are corrected in association with focusing and zooming. The displaying of the visible-light image is continued even during the detection of Raman scattering.Type: GrantFiled: August 21, 2014Date of Patent: January 22, 2019Assignee: Rohm Co., Ltd.Inventors: Hidemi Takasu, Toshihisa Maeda, Masahide Tanaka, Takuji Maekawa
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Patent number: 10120943Abstract: A preference-information gathering system is capable of gathering information on every commodity and/or every service, which are each of interest to a user, as user's preference information. The preference-information gathering system includes a user portable terminal capable of storing a user identifier uniquely identifying the user, an information searching apparatus and a preference-information management apparatus for managing the information on preferences with the user. The information searching apparatus has a search-information inputting unit for requesting a user to enter search information to be used in a process to search for information desired by the user and a user-identifier acquisition unit for acquiring a user identifier.Type: GrantFiled: December 11, 2013Date of Patent: November 6, 2018Assignee: Sony CorporationInventors: Kimiko Tsurumaki, Takuji Maekawa, Kotaro Jinushi, Hirokazu Tanaka
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Patent number: 9496433Abstract: The inventive photoelectric conversion device includes a substrate, a lower electrode layer provided on the substrate, a CIGS compound semiconductor layer provided on the lower electrode layer as covering the lower electrode layer, and a transparent electrode layer provided on the compound semiconductor layer, wherein the compound semiconductor layer has a maximum Ga content variation of not less than 5% as measured in a layer thickness direction, and a maximum In content variation of not less than 6% as measured in the layer thickness direction.Type: GrantFiled: October 10, 2013Date of Patent: November 15, 2016Assignees: ROHM CO., LTD., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Takuji Maekawa, Shigeru Niki, Shogo Ishizuka, Hajime Shibata
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Publication number: 20160077008Abstract: A target is irradiated in a time-shared manner with a visible-light-range illumination light source and an infrared laser beam for Raman scattering, and a target image is formed with an image-capturing lens on a CIGS image sensor provided with a visible-light-range filter, a narrow-band infrared filter for Raman-scattered light measurement, and a near-band reference narrow-band infrared filter that does not let Raman-scattered light pass through. In a preliminary measurement, a plurality of normal sections are measured and averaged, and by using the same as a reference, an actual measurement of Raman scattering is performed. In displaying a visible-light image with the CIGS image sensor, superimposed display is performed to specify sections where Raman scattering is detected, and superimposed display positions are corrected in association with focusing and zooming. The displaying of the visible-light image is continued even during the detection of Raman scattering.Type: ApplicationFiled: August 21, 2014Publication date: March 17, 2016Inventors: Hidemi Takasu, Toshihisa Maeda, Masahide Tanaka, Takuji Maekawa
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Publication number: 20150303330Abstract: The inventive photoelectric conversion device includes a substrate, a lower electrode layer provided on the substrate, a CIGS compound semiconductor layer provided on the lower electrode layer as covering the lower electrode layer, and a transparent electrode layer provided on the compound semiconductor layer, wherein the compound semiconductor layer has a maximum Ga content variation of not less than 5% as measured in a layer thickness direction, and a maximum In content variation of not less than 6% as measured in the layer thickness direction.Type: ApplicationFiled: October 10, 2013Publication date: October 22, 2015Applicants: ROHM CO., LTD., National Institute of Advanced Industrial science and TechnologyInventors: Takuji MAEKAWA, Shigeru NIKI, Shogo ISHIZUKA, Hajime SHIBATA