Abstract: An analyzing device mixes a sample liquid with a reagent by rotation of the analyzing device about a rotation center to generate a centrifugal force. A measurement cell is formed so as to extend in a direction along which the centrifugal force is applied, and a capillary area to which the sample liquid is sucked by a capillary force is formed on one of the side walls of the measurement cell, the side walls being arranged in a rotational direction. The capillary area extends from the outer periphery position to the inner periphery of the measurement cell, thereby reducing the size of the analyzing device. Further, the sample liquid in the measurement cell is sucked to the capillary area by slowing or stopping a rotation, and then the rotation is accelerated to return the sample liquid in the capillary area to the measurement cell.

Abstract: A gate lead wiring and an electrical conductor connecting the gate lead wiring to a protective diode are arranged in a straight line without bending along one and the same side of the chip. A first gate electrode layer extending on the gate lead wiring and the electrical conductor, which connects them to the protective diode, has one bent portion or no bent portion. Further, the protective diode is arranged adjacent to the electrical conductor or the gate lead wiring, and a portion of the protective diode is arranged in close proximity to a gate pad portion.

Abstract: A two-layer electrode structure is provided. A protection diode is provided not to overlap a gate pad portion. Cells and a first one of source electrode layers can be provided below the gate pad portion, so that the differences in resistance among various points in the source electrode layers can be decreased. In addition, the protection diode is positioned adjacent to a device region and at an end portion, of a chip, outward of the device region in such a way as to be in the closest proximity to the gate pad portion. A larger device region with efficient transistor operation can thus be secured, and the resistance of the first source electrode layer below a wiring portion can be reduced.

Abstract: A gate lead wiring and an electrical conductor connecting the gate lead wiring to a protective diode are arranged in a straight line without bending along one and the same side of the chip. A first gate electrode layer extending on the gate lead wiring and the electrical conductor, which connects them to the protective diode, has one bent portion or no bent portion. Further, the protective diode is arranged adjacent to the electrical conductor or the gate lead wiring, and a portion of the protective diode is arranged in close proximity to a gate pad portion.

Abstract: A measurement cell (40a) is formed so as to extend in a direction along which a centrifugal force is applied, and a capillary area (47a) to which a sample liquid is sucked by a capillary force is formed on one of the side walls of the measurement cell (40a), the side walls being arranged in a rotational direction. The capillary area (47a) extends from the outer periphery position to the inner periphery of the measurement cell (40a), thereby reducing the size of an analyzing device. Further, the sample liquid in the measurement cell (40a) is sucked to the capillary area (47a) by slowing or stopping a rotation, and then the rotation is accelerated to return the sample liquid in the capillary area (47a) to the measurement cell (40a). It is therefore possible to achieve a sufficient agitating effect and conduct measurement with a small quantity of sample liquid.

Abstract: Provided is a semiconductor device in which a high concentration n type impurity region to be a conductive path and a drain electrode are disposed in an outer circumferential end of the chip to be an inactive region as a device region. Thereby, an up-drain structure is obtained without reducing the device region or without increasing the size of a semiconductor chip. The provided n type impurity region and drain electrode causes a depletion layer of a substrate to be terminated without needing an additional conventional annular region or shield metal. This is because the n type impurity region and the drain electrode also function as the annular region and the shield metal, respectively. With this configuration, a MOSFET with the up-drain structure having necessary components is obtained, while avoiding a reduction of the device region or an increase of the chip area.

Abstract: A two-layer electrode structure is provided. A protection diode is provided not to overlap a gate pad portion. Cells and a first one of source electrode layers can be provided below the gate pad portion, so that the differences in resistance among various points in the source electrode layers can be decreased. In addition, the protection diode is positioned adjacent to a device region and at an end portion, of a chip, outward of the device region in such a way as to be in the closest proximity to the gate pad portion. A larger device region with efficient transistor operation can thus be secured, and the resistance of the first source electrode layer below a wiring portion can be reduced.

Abstract: Provided is a semiconductor device in which a high concentration n type impurity region to be a conductive path and a drain electrode are disposed in an outer circumferential end of the chip to be an inactive region as a device region. Thereby, an up-drain structure is obtained without reducing the device region or without increasing the size of a semiconductor chip. The provided n type impurity region and drain electrode causes a depletion layer of a substrate to be terminated without needing an additional conventional annular region or shield metal. This is because the n type impurity region and the drain electrode also function as the annular region and the shield metal, respectively. With this configuration, a MOSFET with the up-drain structure having necessary components is obtained, while avoiding a reduction of the device region or an increase of the chip area.

Abstract: In a semiconductor device having a bonding wireless structure, a preform material is used for electrically connecting a metal plate serving as a connection with an electrode layer of a semiconductor chip. Thus, a multilayered metal layer needs to be provided in a junction part between the preform material and a first electrode layer, but has a problem of a variation in electrical characteristics and characteristic fluctuations in a temperature cycling test and the like. A metal layer mainly made of titanium is formed with a thickness of 1000 ?, as a bottom layer (a first metal layer in contact with an electrode layer of a semiconductor chip) in a multilayered metal layer with an electron impact heating deposition method. Thus, the film quality of the Ti layer is improved compared with the conventional structure, which minimizes variations in electrical characteristics and characteristic fluctuations in the multilayered metal layer.