Patents by Inventor Takuji Nakazono

Takuji Nakazono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Thin film transistor and method of manufacturing the same
    Publication number: 20010002047
    Abstract: A thin film transistor of this invention has a structure obtained by sequentially stacking, on an insulating substrate, a silicon nitride film, a silicon oxide film, a polysilicon thin film with a channel region and source and drain regions facing each other via the channel region, an insulating film, and a gate electrode. The boron concentration decreases from the channel region toward the silicon nitride film in the silicon oxide film region between the channel region and the silicon nitride film. The silicon oxide film region between the channel region and the silicon nitride film is made up of a first region which is in contact with the channel region and has a boron concentration of 1×1016 atoms/cm3 or more, and a second region between the first region and the silicon nitride film, which has a boron concentration of less than 1×1016 atoms/cm3. The first region has a thickness of 200 Å or less.
    Type: Application
    Filed: January 18, 2001
    Publication date: May 31, 2001
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Mitsuaki Suzuki, Shinichi Kamagami, Takuji Nakazono
  • Thin film transistor and method of manufacturing the same
    Patent number: 6201260
    Abstract: A thin film transistor of this invention has a structure obtained by sequentially stacking, on an insulating substrate, a silicon nitride film, a silicon oxide film, a polysilicon thin film with a channel region and source and drain regions facing each other via the channel region, an insulating film, and a gate electrode. The boron concentration decreases from the channel region toward the silicon nitride film in the silicon oxide film region between the channel region and the silicon nitride film. The silicon oxide film region between the channel region and the silicon nitride film is made up of a first region which is in contact with the channel region and has a boron concentration of 1×1016 atoms/cm3 or more, and a second region between the first region and the silicon nitride film, which has a boron concentration of less than 1×1016 atoms/cm3. The first region has a thickness of 200 Å or less.
    Type: Grant
    Filed: September 14, 1998
    Date of Patent: March 13, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuaki Suzuki, Shinichi Kamagami, Takuji Nakazono
  • Thermal print head in which a series of semiconductor chips are electrically connected to each other
    Patent number: 5280304
    Abstract: In an image reading apparatus, first and second semiconductor chips are arranged in series on a transparent insulative base. The semiconductor chips are covered by a protective layer and have conductive pads located both side of the series arrangement of the chips. A traveling path in which a document passes is defined on the protective layer between the pads.
    Type: Grant
    Filed: August 25, 1992
    Date of Patent: January 18, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hajime Sato, Takuji Nakazono, Hiroki Nakamura
  • Image reading apparatus in which a series of semiconductor chips are electrically connected to each other
    Patent number: 5260813
    Abstract: In an image reading apparatus, first and second semiconductor chips are arranged in series on a transparent insulative base. The semiconductor chips are covered by a protective layer and have conductive pads located both side of the series arrangement of the chips. A traveling path in which a document passes is defined on the protective layer between the pads.
    Type: Grant
    Filed: March 7, 1991
    Date of Patent: November 9, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hajime Sato, Takuji Nakazono, Hiroki Nakamura