Patents by Inventor Takuji Onuma
Takuji Onuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11069631Abstract: A semiconductor die includes a plurality of alternating stacks of insulating layers and electrically conductive layers that are located over a substrate and that laterally extend along a first horizontal direction and that are laterally spaced apart along a second horizontal direction which is perpendicular to the first horizontal direction, a plurality of sets of memory stack structures extending through the plurality of alternating stacks, and a plurality of nested seal ring structures which include a first seal ring structure comprising having a first seal ring width between an inner sidewall and an outer sidewall thereof, and a second seal ring structure having a second seal ring width between an inner sidewall and an outer sidewall thereof, such that the first seal ring width is less than the second seal ring width.Type: GrantFiled: October 7, 2019Date of Patent: July 20, 2021Assignee: SANDISK TECHNOLOGIES LLCInventor: Takuji Onuma
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Publication number: 20210104473Abstract: A semiconductor die includes a plurality of alternating stacks of insulating layers and electrically conductive layers that are located over a substrate and that laterally extend along a first horizontal direction and that are laterally spaced apart along a second horizontal direction which is perpendicular to the first horizontal direction, a plurality of sets of memory stack structures extending through the plurality of alternating stacks, and a plurality of nested seal ring structures which include a first seal ring structure comprising having a first seal ring width between an inner sidewall and an outer sidewall thereof, and a second seal ring structure having a second seal ring width between an inner sidewall and an outer sidewall thereof, such that the first seal ring width is less than the second seal ring width.Type: ApplicationFiled: October 7, 2019Publication date: April 8, 2021Inventor: Takuji ONUMA
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Patent number: 8982648Abstract: An antifuse comprised of an NMOS transistor or an NMOS capacitor includes a first terminal coupled to a gate electrode, a second terminal coupled to a diffusion layer, and a gate insulating film interposed between the gate electrode and the diffusion layer. A programming circuit includes a first programming circuit which has first current drive capability and which performs first programming operation and a second programming circuit which has second current drive capability larger than the first current drive capability and which performs second programming operation to follow the first programming operation. In the first programming operation, the first programming circuit breaks down the gate insulating film by applying a first programming voltage between the first terminal and the second terminal. In the second programming operation, the second programming circuit applies a second programming voltage lower than the first programming voltage between the first terminal and the second terminal.Type: GrantFiled: July 28, 2011Date of Patent: March 17, 2015Assignee: Renesas Electronics CorporationInventors: Takuji Onuma, Kenichi Hidaka, Hiromichi Takaoka, Yoshitaka Kubota, Hiroshi Tsuda
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Patent number: 8675385Abstract: A first semiconductor device is formed over a substrate and includes a first insulation film, a first electrode, and a first diffusion layer. A second semiconductor device is formed over a substrate and includes a second insulation film, a second electrode, and a second diffusion layer. The second electrode is coupled to the first electrode. A control transistor allows one of a source and a drain to be coupled to the first electrode and the second electrode, allows the other one of the source and the drain to be coupled to a bit line, and allows a gate electrode to be coupled to a word line. A first potential control line is coupled to the first diffusion layer and controls a potential of the first diffusion layer. A second potential control line is coupled to the second diffusion layer and controls a potential of the second diffusion layer.Type: GrantFiled: June 24, 2011Date of Patent: March 18, 2014Assignee: Renesas Electronics CorporationInventors: Hiromichi Takaoka, Kenichi Hidaka, Hiroshi Tsuda, Kiyokazu Ishige, Yoshitaka Kubota, Takuji Onuma
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Patent number: 8592942Abstract: A non-volatile semiconductor memory device having a memory cell in which operating potentials are few and the scale of the peripheral circuitry is reduced includes a select transistor having a source/drain on both sides of a channel of a semiconductor substrate and having a gate electrode disposed on the channel via a thick gate insulating film; an element isolation region formed on the semiconductor substrate in an area adjacent to the select transistor; an antifuse adjacent to the element isolation region, having a lower electrode formed on the semiconductor substrate and having an upper electrode disposed on the semiconductor substrate in an area between the element isolation region and lower electrode via a thin gate insulating film; and a connection contact electrically connecting the source and upper electrode and contacting the source and the upper electrode.Type: GrantFiled: January 16, 2009Date of Patent: November 26, 2013Assignee: Renesas Electronics CorporationInventors: Noriaki Kodama, Kenichi Hidaka, Hiroyuki Kobatake, Takuji Onuma
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Patent number: 8530949Abstract: An antifuse whose internal written information cannot be analyzed even by utilizing methods to determine whether there is a charge-up in the electrodes. The antifuse includes a gate insulation film, a gate electrode, and a first diffusion layer. A second diffusion layer is isolated from the first diffusion layer by way of a device isolator film, and is the same conduction type as the first diffusion layer. The gate wiring is formed as one integrated piece with the gate electrode, and extends over the device isolator film. A common contact couples the gate wiring to the second diffusion layer. The gate electrode is comprised of semiconductor material such as polysilicon that is doped with impurities of the same conduction type as the first diffusion layer. The second diffusion layer is coupled only to the common contact.Type: GrantFiled: September 30, 2011Date of Patent: September 10, 2013Assignee: Renesas Electronics CorporationInventors: Takuji Onuma, Kenichi Hidaka, Hiromichi Takaoka, Yoshitaka Kubota, Hiroshi Tsuda, Kiyokazu Ishige
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Patent number: 8519508Abstract: A semiconductor device has a conventional NMOS transistor and an NMOS transistor functioning as an anti-fuse element and having an n type channel region. The conventional NMOS transistor is equipped with an n type extension region and a p type pocket region, while the anti-fuse element is not equipped with an extension region and a pocket region. This makes it possible to improve the performance of the transistor and at the same time improve the characteristics of the anti-fuse element after breakdown of its gate dielectric film.Type: GrantFiled: November 3, 2010Date of Patent: August 27, 2013Assignee: Renesas Electronics CorporationInventors: Yoshitaka Kubota, Hiroshi Tsuda, Kenichi Hidaka, Takuji Onuma, Hiromichi Takaoka
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Patent number: 8486836Abstract: A semiconductor device including: a substrate; an insulating film formed over the substrate; a copper interconnect, having a plurality of hillocks formed over the surface thereof, buried in the insulating film; a first insulating interlayer formed over the insulating film and the copper interconnect; a second insulating interlayer formed over the first insulating interlayer; and an electroconductive layer formed over the second insulating interlayer, wherein the top surface of at least one hillock highest of all hillocks is brought into contact with the lower surface of the second insulating interlayer is provided.Type: GrantFiled: September 8, 2011Date of Patent: July 16, 2013Assignee: Renesas Electronics CorporationInventors: Daisuke Oshida, Toshiyuki Takewaki, Takuji Onuma, Koichi Ohto
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Patent number: 8361886Abstract: A method for programming an anti-fuse element in which the ratio between current values before and after writing is increased to ensure accuracy in making a judgment about how writing has been performed on the anti-fuse element. The method for programming the anti-fuse element as a transistor includes the steps of applying a prescribed gate voltage to a gate electrode to break down a gate dielectric film, and moving the silicide material of a silicide layer formed on a surface of at least one of a first impurity diffusion region and a second impurity diffusion region, into the gate dielectric film in order to couple the gate electrode with at least the one of the first impurity diffusion region and the second impurity diffusion region electrically through the silicide material.Type: GrantFiled: December 2, 2010Date of Patent: January 29, 2013Assignee: Renesas Electronics CorporationInventors: Yoshitaka Kubota, Takuji Onuma
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Patent number: 8329584Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.Type: GrantFiled: June 2, 2011Date of Patent: December 11, 2012Assignee: Renesas Electronics CorporationInventors: Toshiyuki Takewaki, Manabu Iguchi, Daisuke Oshida, Hironori Toyoshima, Masayuki Hiroi, Takuji Onuma, Hiroaki Nanba, Ichiro Honma, Mieko Hasegawa, Yasuaki Tsuchiya, Toshiji Taiji, Takaharu Kunugi
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Patent number: 8259528Abstract: A semiconductor memory device includes a first anti-fuse element and a second anti-fuse element, respectively composed of a transistor, wherein the first anti-fuse element and the second anti-fuse element are configured so as to be concomitantly programmable, respectively formed in P-wells on a substrate, and the adjacent P-wells are isolated by N-wells of an opposite conductivity type, formed therebetween.Type: GrantFiled: September 28, 2010Date of Patent: September 4, 2012Assignee: Renesas Electronics CorporationInventors: Noriaki Kodama, Takuji Onuma
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Publication number: 20120080736Abstract: An antifuse whose internal written information cannot be analyzed even by utilizing methods to determine whether there is a charge-up in the electrodes. The antifuse includes a gate insulation film, a gate electrode, and a first diffusion layer. A second diffusion layer is isolated from the first diffusion layer by way of a device isolator film, and is the same conduction type as the first diffusion layer. The gate wiring is formed as one integrated piece with the gate electrode, and extends over the device isolator film. A common contact couples the gate wiring to the second diffusion layer. The gate electrode is comprised of semiconductor material such as polysilicon that is doped with impurities of the same conduction type as the first diffusion layer. The second diffusion layer is coupled only to the common contact.Type: ApplicationFiled: September 30, 2011Publication date: April 5, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Takuji ONUMA, Kenichi HIDAKA, Hiromichi TAKAOKA, Yoshitaka KUBOTA, Hiroshi TSUDA, Kiyokazu ISHIGE
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Publication number: 20120044741Abstract: A first semiconductor device is formed over a substrate and includes a first insulation film, a first electrode, and a first diffusion layer. A second semiconductor device is formed over a substrate and includes a second insulation film, a second electrode, and a second diffusion layer. The second electrode is coupled to the first electrode. A control transistor allows one of a source and a drain to be coupled to the first electrode and the second electrode, allows the other one of the source and the drain to be coupled to a bit line, and allows a gate electrode to be coupled to a word line. A first potential control line is coupled to the first diffusion layer and controls a potential of the first diffusion layer. A second potential control line is coupled to the second diffusion layer and controls a potential of the second diffusion layer.Type: ApplicationFiled: June 24, 2011Publication date: February 23, 2012Applicant: Renesas Electronics CorporationInventors: Hiromichi Takaoka, Kenichi Hidaka, Hiroshi Tsuda, Kiyokazu Ishige, Yoshitaka Kubota, Takuji Onuma
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Publication number: 20120026810Abstract: An antifuse comprised of an NMOS transistor or an NMOS capacitor includes a first terminal coupled to a gate electrode, a second terminal coupled to a diffusion layer, and a gate insulating film interposed between the gate electrode and the diffusion layer. A programming circuit includes a first programming circuit which has first current drive capability and which performs first programming operation and a second programming circuit which has second current drive capability larger than the first current drive capability and which performs second programming operation to follow the first programming operation. In the first programming operation, the first programming circuit breaks down the gate insulating film by applying a first programming voltage between the first terminal and the second terminal. In the second programming operation, the second programming circuit applies a second programming voltage lower than the first programming voltage between the first terminal and the second terminal.Type: ApplicationFiled: July 28, 2011Publication date: February 2, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Takuji ONUMA, Kenichi HIDAKA, Hiromichi TAKAOKA, Yoshitaka KUBOTA, Hiroshi TSUDA
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Publication number: 20110318900Abstract: A semiconductor device including: a substrate; an insulating film formed over the substrate; a copper interconnect, having a plurality of hillocks formed over the surface thereof, buried in the insulating film; a first insulating interlayer formed over the insulating film and the copper interconnect; a second insulating interlayer formed over the first insulating interlayer; and an electroconductive layer formed over the second insulating interlayer, wherein the top surface of at least one hillock highest of all hillocks is brought into contact with the lower surface of the second insulating interlayer is provided.Type: ApplicationFiled: September 8, 2011Publication date: December 29, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Daisuke OSHIDA, Toshiyuki TAKEWAKI, Takuji ONUMA, Koichi OHTO
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Patent number: 8030737Abstract: A semiconductor device including: a substrate; an insulating film formed over the substrate; a copper interconnect, having a plurality of hillocks formed over the surface thereof, buried in the insulating film; a first insulating interlayer formed over the insulating film and the copper interconnect; a second insulating interlayer formed over the first insulating interlayer; and an electroconductive layer formed over the second insulating interlayer, wherein the top surface of at least one hillock highest of all hillocks is brought into contact with the lower surface of the second insulating interlayer is provided.Type: GrantFiled: January 10, 2008Date of Patent: October 4, 2011Assignee: Renesas Electronics CorporationInventors: Daisuke Oshida, Toshiyuki Takewaki, Takuji Onuma, Koichi Ohto
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Publication number: 20110230051Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.Type: ApplicationFiled: June 2, 2011Publication date: September 22, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Toshiyuki TAKEWAKI, Manabu IGUCHI, Daisuke OSHIDA, Hironori TOYOSHIMA, Masayuki HIROI, Takuji ONUMA, Hiroaki NANBA, Ichiro HONMA, Mieko HASEGAWA, Yasuaki TSUCHIYA, Toshiji TAIJI, Takaharu KUNUGI
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Patent number: 7955980Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.Type: GrantFiled: August 18, 2009Date of Patent: June 7, 2011Assignee: Renesas Electronics CorporationInventors: Toshiyuki Takewaki, Manabu Iguchi, Daisuke Oshida, Hironori Toyoshima, Masayuki Hiroi, Takuji Onuma, Hiroaki Nanba, Ichiro Honma, Mieko Hasegawa, Yasuaki Tsuchiya, Toshiji Taiji, Takaharu Kunugi
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Publication number: 20110127591Abstract: A method for programming an anti-fuse element in which the ratio between current values before and after writing is increased to ensure accuracy in making a judgment about how writing has been performed on the anti-fuse element. The method for programming the anti-fuse element as a transistor includes the steps of applying a prescribed gate voltage to a gate electrode to break down a gate dielectric film, and moving the silicide material of a silicide layer formed on a surface of at least one of a first impurity diffusion region and a second impurity diffusion region, into the gate dielectric film in order to couple the gate electrode with at least the one of the first impurity diffusion region and the second impurity diffusion region electrically through the silicide material.Type: ApplicationFiled: December 2, 2010Publication date: June 2, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yoshitaka KUBOTA, Takuji ONUMA
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Publication number: 20110122672Abstract: A non-volatile semiconductor memory device having a memory cell in which operating potentials are few and the scale of the peripheral circuitry is reduced includes a select transistor having a source/drain on both sides of a channel of a semiconductor substrate and having a gate electrode disposed on the channel via a thick gate insulating film; an element isolation region formed on the semiconductor substrate in an area adjacent to the select transistor; an antifuse adjacent to the element isolation region, having a lower electrode formed on the semiconductor substrate and having an upper electrode disposed on the semiconductor substrate in an area between the element isolation region and lower electrode via a thin gate insulating film; and a connection contact electrically connecting the source and upper electrode and contacting the source and the upper electrode.Type: ApplicationFiled: January 26, 2011Publication date: May 26, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Noriaki Kodama, Kenichi Hidaka, Hiroyuki Kobatake, Takuji Onuma