Patents by Inventor Takuji Tanigami

Takuji Tanigami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5742541
    Abstract: A non-volatile semiconductor memory includes a plurality of memory cells. Each memory cell includes N-type source and drain regions formed in a P-well on a semiconductor substrate, a floating gate formed on the P-well with a tunnel oxide film therebetween, and a control gate formed on the floating gate with an interpoly dielectric film therebetween. The memory has a plurality of bit lines, a plurality of word lines and a source line. The source region of each memory cell is connected to the source line. The drain region of each memory cell is connected to one of the word lines. The memory cell is written to, erased, or read by selectively supplying suitable voltages to the source, bit, and word lines connected thereto.
    Type: Grant
    Filed: December 28, 1995
    Date of Patent: April 21, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takuji Tanigami, Shinichi Sato
  • Patent number: 5708600
    Abstract: There is provided a method for writing a multiple value into a nonvolatile memory capable of writing multiple value data into a floating gate type memory cell in an equal time even when the data are varied. With a specified voltage applied to a control gate of a memory cell, a drain voltage which is varied according to each of data values "11", "10" and "01" to a drain so that a write time required for setting a varied threshold voltage is equalized. By moving electrons between a floating gate and a drain through a gate insulating film, the threshold voltage of the memory cell is set.
    Type: Grant
    Filed: October 1, 1996
    Date of Patent: January 13, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kenji Hakozaki, Shinichi Sato, Takuji Tanigami