Patents by Inventor Takuji Uneyama

Takuji Uneyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Self-synchronous transfer control circuit and data driven information processing device using the same
    Patent number: 7051194
    Abstract: When an instruction decoder decodes an instruction code included in packet data, a copy flag and copy number information are provided to a self-synchronous transfer control circuit. In the self-synchronous transfer control circuit, when a data transfer enabling signal is applied from a C element in a subsequent stage, a node number manipulation circuit manipulates a node number to make copies such that packets can be distinguished from each other, and then data is transferred from a pipeline register to a pipeline register in a subsequent stage.
    Type: Grant
    Filed: March 21, 2001
    Date of Patent: May 23, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takuji Uneyama, Motoki Takase, Tsuyoshi Muramatsu
  • Self-synchronous FIFO memory device having high access efficiency, and system provided with interface for data transfer using the same
    Patent number: 6941434
    Abstract: An arbitration circuit adjusts timings of a write request signal from a first external device and a read request signal from a second external device. An RAM performs data write/data read in response to the external write request/read request. A next-state function is provided, which has a function to calculate a write address/read address to be input to the RAM in response to the external write request/read request, and a function to accurately count data stored in a FIFO.
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: September 6, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takuji Uneyama, Manabu Onozaki
  • Self-synchronous FIFO memory device having high access efficiency, and system provided with interface for data transfer using the same
    Publication number: 20030172242
    Abstract: An arbitration circuit adjusts timings of a write request signal from a first external device and a read request signal from a second external device. An RAM performs data write/data read in response to the external write request/read request. A next-state function is provided, which has a function to calculate a write address/read address to be input to the RAM in response to the external write request/read request, and a function to accurately count data stored in a FIFO.
    Type: Application
    Filed: March 3, 2003
    Publication date: September 11, 2003
    Inventors: Takuji Uneyama, Manabu Onozaki
  • Self-synchronous transfer control circuit and data driven information processing device using the same
    Publication number: 20010028629
    Abstract: When an instruction decoder decodes an instruction code included in packet data, a copy flag and copy number information are provided to a self-synchronous transfer control circuit. In the self-synchronous transfer control circuit, when a data transfer enabling signal is applied from a C element in a subsequent stage, a node number manipulation circuit manipulates a node number to make copies such that packets can be distinguished from each other, and then data is transferred from a pipeline register to a pipeline register in a subsequent stage.
    Type: Application
    Filed: March 21, 2001
    Publication date: October 11, 2001
    Inventors: Takuji Uneyama, Motoki Takase, Tsuyoshi Muramatsu