Abstract: An image coding device is provided that includes an image coding unit which codes image data, a binarization unit which binarizes the coded data, an intermediate buffer, an accumulated amount measuring unit which measures an amount of data in the intermediate buffer, and an I_PCM judging unit which compares the measured amount of data with a threshold. A buffer input selection unit is also provided which causes the intermediate buffer to accumulate next binary data when the amount of the data does not exceed the threshold and causes the intermediate buffer to accumulate next I_PCM data when the amount of the data exceeds the threshold. In addition, the device includes an arithmetic coding unit that arithmetically codes the binary data accumulated in the intermediate buffer and an output selection unit outputs the arithmetically coded data or the I_PCM data.

Abstract: An image coding apparatus (100) which reduces buffer capacity to a minimum and includes an image coding processing unit (110) which generates intermediate data by executing a part of a process in the coding on the image data; a packetizing unit (120) which generates an image stream by executing a process other than the part of the process in the coding on the intermediate data, such as for example arithmetic coding, and packetizes the generated image stream in synchronization with the image stream generation process.

Abstract: An image coding device is provided that includes an image coding unit which codes image data, a binarization unit which binarizes the coded data, an intermediate buffer, an accumulated amount measuring unit which measures an amount of data in the intermediate buffer, and an I_PCM judging unit which compares the measured amount of data with a threshold. A buffer input selection unit is also provided which causes the intermediate buffer to accumulate next binary data when the amount of the data does not exceed the threshold and causes the intermediate buffer to accumulate next I_PCM data when the amount of the data exceeds the threshold. In addition, the device includes an arithmetic coding unit that arithmetically codes the binary data accumulated in the intermediate buffer and an output selection unit outputs the arithmetically coded data or the I_PCM data.

Abstract: A tag storing unit stores, in a plurality of entries, a plurality of tags corresponding to a plurality of addresses, a parity bit of each of the tags, and a reverse bit obtained by reversing the parity bit. A data storing unit stores a plurality of data corresponding to the tags in a plurality of entries. A comparing unit compares an address for search with a tag of each of the entries. A determining unit performs an OR-operation on contents stored in a plurality of entries when a multiple hit occurs from a comparison by the comparing unit, and determines a cause of the multiple hit based on a parity bit and a reverse bit obtained after the OR-operation.

Abstract: Provided is an image coding device in which entropy coding is applied to binarized data, thereby processing image data at a high speed.

Abstract: An image coding apparatus that makes possible the parallelization of intra prediction, and outputs coded data that can be decoded by an image decoding apparatus compliant with the H.264 standard. The image coding apparatus performs orthogonal transformation, quantization, inverse quantization, inverse orthogonal transformation, and intra prediction on all blocks obtained when a single macroblock is divided into plural blocks, and includes: a predicted block control unit that causes all of the blocks to be intra predicted using at least one of the intra prediction modes specified in the H.264 standard on at least some of the blocks, in an order different from the raster scan order specified in the H.264 standard; and an sorting buffer that outputs, in the raster scan order, all the blocks intra predicted under the control of the predicted block control unit.

Abstract: The coding apparatus according to the present invention is a coding apparatus which codes data regarding a moving picture, and includes: a DCT coefficient advanced-coding unit which performs advanced-coding on multivalued data representing a quantized DCT coefficient or a motion vector, so as to reduce the bit length of binary data obtained by binarizing the multivalued data; an advanced-coded coefficient/binary coefficient conversion unit which converts the advanced-coded data obtained by the DCT coefficient advanced-coding unit into the binary data; and an arithmetic coding unit which performs arithmetic coding on the binary data obtained by the advanced-coded coefficient/binary coefficient conversion unit.

Abstract: The present invention provides a video encoding device in which a capacity of a binary data storing unit is small, a size of the video encoding device is small, a video signal can be processed in real time, and reduction in quality of images generated from the eventually obtained data can be prevented. The video encoding device according to the present invention includes: a video encoding unit which encodes a video signal; a binarization unit which binarizes an encoded value obtained from the video encoding unit; and an entropy encoding unit which subjects entropy encoding to binary data obtained from the binarization unit.

Abstract: The resolution, frame rate, or both can be improved when imaging moving subjects in an imaging apparatus using a CMOS image sensor. The imaging apparatus has an image sensor having a two-dimensional array of pixels. Each of the pixels includes an element operable to produce an electric charge by photoelectrically converting light from an imaged subject and a part operable to accumulate the produced charge and output an accumulated charge or a signal representing the accumulated charge. The imaging apparatus also has an area control unit operable to define a specified area of the image sensor containing a plurality of pixels and an area density control unit operable to specify a density of pixels read from the specified area defined by the area control unit.

Abstract: A MOS image sensor and an imaging apparatus using this image sensor enable controlling sensor driving with a high degree of freedom using a simple control circuit design and minimal wiring lines. The light reception unit of the image sensor in this imaging apparatus is segmented into a plurality of areas and conventional shift registers are constructed in multiple layers, thus enabling controlling the multiple sensor areas by means of a relatively simple circuit design. The imaging apparatus can thus locally change exposure and imaging conditions in parts of a single frame. Problems due to underexposure and overexposure are thus suppressed, and images with a wide dynamic range can be captured.

Abstract: When a method or apparatus of assuring simultaneous exposure, such as a mechanical shutter, is not provided with a MOS imaging sensor, moving subjects are distorted with a MOS image sensor when capturing a still image of a fast-moving subject because imaging and reading are not simultaneous across the MOS sensor. Changing the MOS sensor exposure sequence and reading sequence, and interpolating the read data, change and correct the read sequence line by line when imaging a high resolution moving image, and thus improve distortion in moving subjects.

Abstract: A first table stores operand data for translation of operand virtual address into a physical address. A second table stores instruction data for translation of instruction virtual address into a physical address. The first and the second tables are formed in one memory. If operand access and instruction access are generated simultaneously, the operand access is executed with priority and the instruction virtual address is held in a wait register after that the instruction access is executed after finishing the operand access based on a wait instruction virtual address.

Abstract: A higher TLB that stores TLB data required for translating a virtual address into a physical address. A higher address translator performs address translation based on the TLB data according to an access. If address translation is not possible, the higher address translator requests a lower address translator to carry out the address translation. The lower address translator performs address translation based on a lower TLB. A shift register outputs a write prohibit signal to prohibit writing of the TLB data to the higher TLB, when write data that is the same as the write data has already been written in the higher TLB.

Abstract: A first table stores operand data for translation of operand virtual address into a physical address. A second table stores instruction data for translation of instruction virtual address into a physical address. The first and the second tables are formed in one memory. If operand access and instruction access are generated simultaneously, the operand access is executed with priority and the instruction virtual address is held in a wait register after that the instruction access is executed after finishing the operand access based on a wait instruction virtual address.

Abstract: A higher TLB that stores TLB data required for translating a virtual address into a physical address. A higher address translator performs address translation based on the TLB data according to an access. If address translation is not possible, the higher address translator requests a lower address translator to carry out the address translation. The lower address translator performs address translation based on a lower TLB. A shift register outputs a write prohibit signal to prohibit writing of the TLB data to the higher TLB, when write data that is the same as the write data has already been written in the higher TLB.