Abstract: A skin state is readily obtained. A method according to one embodiment of the present invention includes identifying a nasal feature of a user; and estimating a skin state of the user based on the nasal feature of the user.

Abstract: A simulation method is a simulation method of a semiconductor device. The semiconductor device includes a first electrode, a second electrode, a semiconductor part located between the first electrode and the second electrode, an insulating member located inside the semiconductor part, a third electrode located inside the insulating member, and a fourth electrode located between the first electrode and the third electrode and located inside the insulating member. The method includes causing a value of a first resistance to change according to a value of a first voltage between the first electrode and the second electrode. The first resistance is connected between the second electrode and the fourth electrode.

Abstract: A semiconductor device includes first and second metallic members, and a semiconductor chip provided on the first metallic member that includes a first electrode, a first semiconductor region of a first conductive type, second semiconductor regions of a second conductive type, third semiconductor regions of the first conductive type, gate electrodes, and a second electrode. The gate electrodes face the second semiconductor regions via ¥ gate insulating layers. The second electrode is electrically connected to the plurality of second semiconductor regions and the plurality of third semiconductor regions. The second metallic member is provided on the semiconductor chip. The semiconductor chip includes a first portion located between the metallic members as viewed in a first direction and a second portion. A thickness of each of the gate insulating layers in the second portion is larger than that of the gate insulating layers in the first portion.

Abstract: A semiconductor device comprises an element region and a terminal region that surrounds the element region. The semiconductor device includes a first semiconductor region having a first conductivity type and a second semiconductor region having a second conductivity type and provided on the first semiconductor region. A third semiconductor region having the first conductivity type is provided on the second semiconductor region. A first electrode is electrically connected to the first semiconductor region. A second electrode is electrically connected to the third semiconductor region. A third and a fourth electrode are disposed in the element region. A distance from the first electrode to the third electrode is less than a distance from the first electrode to the fourth electrode.

Abstract: A semiconductor device includes a first electrode, a first semiconductor layer of a first conductivity type located on the first electrode, a second semiconductor layer of a second conductivity type located on the first semiconductor layer, a third semiconductor layer of the first conductivity type located on a portion of the second semiconductor layer, a second electrode located in the first semiconductor layer, the second semiconductor layer and the third semiconductor layer, the second electrode extending along and around an outer edge of the first semiconductor layer, and spaced from the second semiconductor layer by an insulating film, a wiring located on the third semiconductor layer and connected to the second electrode, and a third electrode connected to the second semiconductor layer and the third semiconductor layer.

Abstract: A semiconductor device comprises an element region and a terminal region that surrounds the element region. The semiconductor device includes a first semiconductor region having a first conductivity type and a second semiconductor region having a second conductivity type and provided on the first semiconductor region. A third semiconductor region having the first conductivity type is provided on the second semiconductor region. A first electrode is electrically connected to the first semiconductor region. A second electrode is electrically connected to the third semiconductor region. A third and a fourth electrode are disposed in the element region. A distance from the first electrode to the third electrode is less than a distance from the first electrode to the fourth electrode.

Abstract: In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type having first and second faces, and a second semiconductor layer of a second conductivity type disposed above the first face of the first semiconductor layer. The device further includes control electrodes facing the first and second semiconductor layers via insulating layers, and extending to a first direction parallel to the first face of the first semiconductor layer, and third semiconductor layers of the first conductivity type and fourth semiconductor layers of the second conductivity type alternately disposed along the first direction above the second semiconductor layer. The device further includes fifth semiconductor layers of the first conductivity type disposed below the second semiconductor layer or disposed at positions surrounded by the second semiconductor layer, the fifth semiconductor layers being arranged separately from one another along the first direction.

Abstract: In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type having first and second faces, and a second semiconductor layer of a second conductivity type disposed above the first face of the first semiconductor layer. The device further includes control electrodes facing the first and second semiconductor layers via insulating layers, and extending to a first direction parallel to the first face of the first semiconductor layer, and third semiconductor layers of the first conductivity type and fourth semiconductor layers of the second conductivity type alternately disposed along the first direction above the second semiconductor layer. The device further includes fifth semiconductor layers of the first conductivity type disposed below the second semiconductor layer or disposed at positions surrounded by the second semiconductor layer, the fifth semiconductor layers being arranged separately from one another along the first direction.

Abstract: In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type having first and second faces, and a second semiconductor layer of a second conductivity type disposed above the first face of the first semiconductor layer. The device further includes control electrodes facing the first and second semiconductor layers via insulating layers, and extending to a first direction parallel to the first face of the first semiconductor layer, and third semiconductor layers of the first conductivity type and fourth semiconductor layers of the second conductivity type alternately disposed along the first direction above the second semiconductor layer. The device further includes fifth semiconductor layers of the first conductivity type disposed below the second semiconductor layer or disposed at positions surrounded by the second semiconductor layer, the fifth semiconductor layers being arranged separately from one another along the first direction.

Abstract: In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type having first and second faces, and a second semiconductor layer of a second conductivity type disposed above the first face of the first semiconductor layer. The device further includes control electrodes facing the first and second semiconductor layers via insulating layers, and extending to a first direction parallel to the first face of the first semiconductor layer, and third semiconductor layers of the first conductivity type and fourth semiconductor layers of the second conductivity type alternately disposed along the first direction above the second semiconductor layer. The device further includes fifth semiconductor layers of the first conductivity type disposed below the second semiconductor layer or disposed at positions surrounded by the second semiconductor layer, the fifth semiconductor layers being arranged separately from one another along the first direction.

Abstract: An upper part of the termination region of the semiconductor substrate, an upper surface of the first diffusion layers and an upper surface of the first oxide film is etched in such a manner that the level of the upper surface of the semiconductor substrate in the termination region including the first oxide film and the first diffusion layers is lower than the level of the upper surface of the semiconductor substrate in the cell region. Then, a second oxide film is formed on the semiconductor substrate. An electrode is formed on the second oxide film so as to extend from the first region toward the cell region to the first diffusion layers in such a manner that the level of an upper surface of the electrode is lower than the level of the upper surface of the semiconductor substrate in the cell region.

Abstract: A trench gate semiconductor device including: a semiconductor layer having a first conductivity type; a first diffusion region having a second conductivity type having a planar structure on the semiconductor layer; a second diffusion region having the first conductivity type positioned selectively on the first diffusion region; a gate electrode provided via a gate insulation film in each first trench facing the second diffusion region and penetrating through the first diffusion region to reach the semiconductor layer; a first semiconductor region of the second conductivity type provided at a position, in the semiconductor layer, apart in a lateral direction from the first diffusion region; a second semiconductor region of the second conductivity type provided at a position, in the first diffusion region, between the adjacent first trenches; and a main electrode in contact with the semiconductor layer and the second diffusion region.

Abstract: There is provided a semiconductor device having a switching element, including a first semiconductor layer including a first, second and third surfaces, a first electrode connected to the first semiconductor layer, a plurality of second semiconductor layers selectively configured on the first surface, a third semiconductor layer configured on the second semiconductor layer, a second electrode configured to be contacted with the second semiconductor layer and the third semiconductor layer, a gate electrode formed over the first semiconductor layer, a first region including a first tale region, a density distribution of crystalline defects being gradually increased therein, a peak region crossing a current path applying to a forward direction in a p-n junction, a second tale region continued from the peak region, and a second region including a third tale region, the density distribution of the crystalline defects being gradually increased therein.

Abstract: There is provided a semiconductor device having a switching element, including a first semiconductor layer including a first, second and third surfaces, a first electrode connected to the first semiconductor layer, a plurality of second semiconductor layers selectively configured on the first surface, a third semiconductor layer configured on the second semiconductor layer, a second electrode configured to be contacted with the second semiconductor layer and the third semiconductor layer, a gate electrode formed over the first semiconductor layer, a first region including a first tale region, a density distribution of crystalline defects being gradually increased therein, a peak region crossing a current path applying to a forward direction in a p-n junction, a second tale region continued from the peak region, and a second region including a third tale region, the density distribution of the crystalline defects being gradually increased therein.

Abstract: In various aspects, a MOSFET may include an active region of a first conductivity type provided on an insulating layer, the active region having a first portion and a second portion, the first portion being thicker than the second portion; a base region of the first conductivity type provided on the insulating layer, the base region having a higher impurity concentration than the first portion of the active region, the base region being in contact with the first portion of the active region and the insulating layer; a drain region of a second conductivity type provided on the insulating layer, the drain region being in contact with the second portion of the active region and the insulating layer, the drain region being spaced from the base region; a source region of the second conductivity type provided on a surface of the base region; a gate insulating layer provided on the source region, the base region, the active region and the drain region; and a gate electrode provided on the gate insulating layer.

Abstract: Disclosed is a trench gate semiconductor device including: a semiconductor layer having a first conductivity type; a first diffusion region having a second conductivity type having a planar structure on the semiconductor layer; a second diffusion region having the first conductivity type positioned selectively on the first diffusion region; a gate electrode provided via a gate insulation film in each first trench facing the second diffusion region and penetrating through the first diffusion region to reach the semiconductor layer; a first semiconductor region of the second conductivity type provided at a position, in the semiconductor layer, apart in a lateral direction from the first diffusion region; a second semiconductor region of the second conductivity type provided at a position, in the first diffusion region, between the adjacent first trenches; and a main electrode in contact with the semiconductor layer and the second diffusion region.

Abstract: In various aspects, a MOSFET may include an active region of a first conductivity type provided on an insulating layer, the active region having a first portion and a second portion, the first portion being thicker than the second portion; a base region of the first conductivity type provided on the insulating layer, the base region having a higher impurity concentration than the first portion of the active region, the base region being in contact with the first portion of the active region and the insulating layer; a drain region of a second conductivity type provided on the insulating layer, the drain region being in contact with the second portion of the active region and the insulating layer, the drain region being spaced from the base region; a source region of the second conductivity type provided on a surface of the base region; a gate insulating layer provided on the source region, the base region, the active region and the drain region; and a gate electrode provided on the gate insulating layer.

Abstract: A semiconductor device comprises: a first main electrode; a second main electrode; a semiconductor base region of a first conductivity type; a gate electrode provided in a trench through an insulating film, the trench being formed to penetrate the semiconductor base region; and a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type provided under the semiconductor base region. A flow of a current between the first and second main electrodes when a voltage of a predetermined direction is applied between these electrodes is controllable in accordance with a voltage applied to the gate electrode. A depleted region extends from a junction between the first and the second semiconductor regions reaching the trench.

Abstract: A semiconductor device comprises a semiconductor substrate; a semiconductor layer provided on the surface of the semiconductor substrate; a base layer provided on the surface of the semiconductor layer; a source layer provided on the surface of the base layer; a trench formed to pass through the source layer, the base layer, and the semiconductor layer from the surface of the source layer, and reaching the semiconductor substrate; a gate electrode provided from the source layer to at least the semiconductor layer within the trench; and an insulator provided between the gate electrode and the base layer so as to fill in the inside of the trench below the gate electrode, the insulator insulating the gate electrode from the base layer, and generating a potential distribution from the gate electrode toward the semiconductor substrate when a voltage is applied to the gate electrode.

Abstract: According to the present invention, there is provided a semiconductor device having, a semiconductor substrate having a surface on which an insulating layer is formed, a first-conductivity-type first semiconductor layer formed on the insulating layer and having a first impurity concentration, a first-conductivity-type second semiconductor region formed in the first semiconductor layer from a surface of the first semiconductor layer to a surface of the insulating layer, and having a concentration higher than the first impurity concentration, a second-conductivity-type third semiconductor region formed in the first semiconductor layer from the surface of the first semiconductor layer to the surface of the insulating layer with a predetermined distance between the second and third semiconductor regions, and having a second impurity concentration, a second-conductivity-type fourth semiconductor region formed in a surface portion of the second semiconductor region, and having a concentration higher than the second