Abstract: The present invention relates to a heterojunction field effect transistor, and the heterojunction field effect transistor includes a barrier layer provided in an upper layer portion of a channel layer of a first nitride semiconductor, being formed of a second nitride semiconductor hetero-joined to the first nitride semiconductor, first and second impurity regions provided, being spaced each other with the barrier layer interposed therebetween, a source electrode and a drain electrode which are provided on the first and second impurity regions, respectively, an insulating film which is so provided as to come into contact with at least a region of the barrier layer excluding an edge portion thereof on the side of the source electrode, a gate insulating film which is in contact with the edge portion of the barrier layer and covers the insulating film, and a gate electrode which is so provided on the gate insulating film.

Abstract: Provided is a technology for obtaining a drain current of a sufficient magnitude in a field effect transistor using a nitride semiconductor. A channel layer that is Alx1Iny1Ga1-x1-y1N is formed on an upper surface of a semiconductor substrate, and on an upper surface of the channel layer, a barrier layer that is Alx2Iny2Ga1-x2-y2N having a band gap larger than that of the channel layer is formed. Then, on an upper surface of the barrier layer, a gate insulating film that is an insulator or a semiconductor and has a band gap larger than that of the barrier layer is at least partially formed, and a gate electrode is formed on an upper surface of the gate insulating film. Then, heat treatment is performed while a positive voltage is applied to the gate electrode.

Abstract: A semiconductor device includes a supporting substrate, a first GaN layer of a first conductivity type provided on the side of a first main surface of the supporting substrate, a second GaN layer of the first conductivity type provided on the first GaN layer, an AlxGa1?xN layer provided on the second GaN layer, a third GaN layer of a second conductivity type provided on the AlxGa1?xN layer, a fourth GaN layer of the first conductivity type provided on the third GaN layer, an insulating film covering a top of the fourth GaN layer, a trench gate reaching the inside of the second GaN layer, a gate electrode, a first main electrode connected to the third GaN layer, and a second main electrode, and the donor concentration of the third GaN layer is lower than that of the fourth GaN layer.

Abstract: A semiconductor device includes a supporting substrate, a first GaN layer of a first conductivity type provided on the side of a first main surface of the supporting substrate, a second GaN layer of the first conductivity type provided on the first GaN layer, an AlxGa1?xN layer provided on the second GaN layer, a third GaN layer of a second conductivity type provided on the AlxGa1?xN layer, a fourth GaN layer of the first conductivity type provided on the third GaN layer, an insulating film covering a top of the fourth GaN layer, a trench gate reaching the inside of the second GaN layer, a gate electrode, a first main electrode connected to the third GaN layer, and a second main electrode, and the donor concentration of the third GaN layer is lower than that of the fourth GaN layer.

Abstract: A first insulating layer is disposed on a second surface of a semiconductor substrate, and has an opening. A second insulating layer is disposed on the second surface and separated from the first insulating layer. A stack includes, in sequence on the second surface, a side n-type epitaxial layer and first and second p-type epitaxial layers that are made of a gallium-nitride-based material. The stack has an outer side wall having a portion formed of the second p-type epitaxial layer, an inner side wall extending from the second insulating layer, and a top surface. The n-type contact layer is disposed on the top surface. The source electrode portion is in contact with the n-type contact layer on the top surface, and is in contact with the second p-type epitaxial layer on the outer side wall. A gate insulating film is disposed on the inner side wall.

Abstract: A substrate is made of gallium-nitride-based material. The n-type layer is disposed on a first surface of the substrate. A p-type layer is disposed on the n-type layer, and constitutes, along with the n-type layer, a semiconductor layer on the first surface of the substrate, the semiconductor layer being provided with a mesa shape having a bottom surface, a side surface, and a top surface. An anode electrode is disposed on the p-type layer. A cathode electrode is disposed on a second surface of the substrate. An insulating film continuously extends over the bottom surface and the top surface to cover the side surface. The top surface is provided with at least one trench. The at least one trench includes a trench filled with the insulating film.

Abstract: Provided is a technology for obtaining a drain current of a sufficient magnitude in a field effect transistor using a nitride semiconductor. A channel layer that is Alx1Iny1Ga1-x1-y1N is formed on an upper surface of a semiconductor substrate, and on an upper surface of the channel layer, a barrier layer that is Alx2Iny2Ga1-x2-y2N having a band gap larger than that of the channel layer is formed. Then, on an upper surface of the barrier layer, a gate insulating film that is an insulator or a semiconductor and has a band gap larger than that of the barrier layer is at least partially formed, and a gate electrode is formed on an upper surface of the gate insulating film. Then, heat treatment is performed while a positive voltage is applied to the gate electrode.

Abstract: A substrate is made of gallium-nitride-based material. The n-type layer is disposed on a first surface of the substrate. A p-type layer is disposed on the n-type layer, and constitutes, along with the n-type layer, a semiconductor layer on the first surface of the substrate, the semiconductor layer being provided with a mesa shape having a bottom surface, a side surface, and a top surface. An anode electrode is disposed on the p-type layer. A cathode electrode is disposed on a second surface of the substrate. An insulating film continuously extends over the bottom surface and the top surface to cover the side surface. The top surface is provided with at least one trench. The at least one trench includes a trench filled with the insulating film.

Abstract: A first insulating layer is disposed on a second surface of a semiconductor substrate, and has an opening. A second insulating layer is disposed on the second surface and separated from the first insulating layer. A stack includes, in sequence on the second surface, a side n-type epitaxial layer and first and second p-type epitaxial layers that are made of a gallium-nitride-based material. The stack has an outer side wall having a portion formed of the second p-type epitaxial layer, an inner side wall extending from the second insulating layer, and a top surface. The n-type contact layer is disposed on the top surface. The source electrode portion is in contact with the n-type contact layer on the top surface, and is in contact with the second p-type epitaxial layer on the outer side wall. A gate insulating film is disposed on the inner side wall.

Abstract: A semiconductor device includes: a substrate; a nitride semiconductor layer on the substrate; a source electrode, a drain electrode and a gate electrode on the nitride semiconductor layer; and a SiN surface protective film covering the nitride semiconductor layer, wherein a composition ratio Si/N of Si and N that form a Si—N bond of the SiN surface protective film is 0.751 to 0.801.

Abstract: A semiconductor device includes: a substrate; a nitride semiconductor layer on the substrate; a source electrode, a drain electrode and a gate electrode on the nitride semiconductor layer; and a SiN surface protective film covering the nitride semiconductor layer, wherein a composition ratio Si/N of Si and N that form a Si—N bond of the SiN surface protective film is 0.751 to 0.

Abstract: A semiconductor device includes an Alx1Ga1-x1N (0?x1?1) barrier layer, and a gate electrode that is disposed on a surface of the Alx1Ga1-x1N (0?x1?1) barrier layer, forms a Schottky junction with the surface of the Alx1Ga1-x1N (0?x1?1) barrier layer, and has an Ni single-layer structure. Annealing processing is performed with respect to the gate electrode at a temperature of 500° C. or above under a nitrogen atmosphere to form a reaction layer between the surface of the Alx1Ga1-x1N (0?x1?1) barrier layer and the gate electrode.

Abstract: The present invention relates to a method for manufacturing a heterojunction semiconductor device including an AlGaN layer, the method including the steps of (a) forming a dummy electrode in a region where a gate electrode is arranged on the AlGaN layer, (b) depositing a dielectric film on the AlGaN layer by exposing side surfaces of the dummy electrode, using a device having anisotropy, (c) forming an opening in the dielectric film by removing the dummy electrode, and (d) forming the gate electrode that extends from inside the opening onto the dielectric film in a vicinity of the opening.

Abstract: A laminate includes a surface on which a gate electrode is provided, and is made of a nitride semiconductor. The laminate includes a first layer having a first band gap, and a second layer provided between the first layer and the surface and having a second band gap which is larger than the first band gap. The first and second layers and form a joint surface by a hetero junction. The surface includes a surface defect density equal to or smaller than 1.7×106 cm?2.

Abstract: The present invention relates to a method for manufacturing a heterojunction semiconductor device including an AlGaN layer, the method including the steps of (a) forming a dummy electrode in a region where a gate electrode is arranged on the AlGaN layer, (b) depositing a dielectric film on the AlGaN layer by exposing side surfaces of the dummy electrode, using a device having anisotropy, (c) forming an opening in the dielectric film by removing the dummy electrode, and (d) forming the gate electrode that extends from inside the opening onto the dielectric film in a vicinity of the opening.

Abstract: The objective of the present invention is to provide a semiconductor device of a hetero-junction field effect transistor that is capable of obtaining a high output and a high breakdown voltage and a manufacturing method of the same. The present invention is a semiconductor device of a hetero junction field effect transistor provided with an AlxGa1-xN channel layer with a composition ratio of Al being x (0<x<1) formed on a substrate, an AlyGa1-yN barrier layer with a composition of Al being y (0<y?1) formed on the channel layer, and source/drain electrodes and a gate electrode formed on the barrier layer, wherein the composition ratio y is larger than the composition ratio x.

Abstract: The objective of the present invention is to provide a semiconductor device of a hetero-junction field effect transistor that is capable of obtaining a high output and a high breakdown voltage and a manufacturing method of the same. The present invention is a semiconductor device of a hetero-junction field effect transistor provided with an AlxGa1-xN channel layer with a composition ratio of Al being x (0<x<1) formed on a substrate, an AlyGa1-yN barrier layer with a composition of Al being y (0<y?1) formed on the channel layer, and source/drain electrodes and a gate electrode formed on the barrier layer, wherein the composition ratio y is larger than the composition ratio x.

Abstract: The objective of the present invention is to provide a semiconductor device of a hetero-junction field effect transistor that is capable of obtaining a high output and a high breakdown voltage and a manufacturing method of the same. The present invention is a semiconductor device of a hetero-junction field effect transistor provided with an AlxGa1-xN channel layer with a composition ratio of Al being x (0<x<1) formed on a substrate, an AlyGa1-yN barrier layer with a composition of Al being y (0<y?1) formed on the channel layer, and source/drain electrodes and a gate electrode formed on the barrier layer, wherein the composition ratio y is larger than the composition ratio x.