Patents by Inventor Takuma Wada

Takuma Wada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11939678
    Abstract: A method of making a semiconductor manufacturing apparatus member includes a step of preparing an aluminum base having an alumite layer having a porous columnar structure at an upper surface thereof. The alumite layer is an anodic oxidation film, and a Young's modulus of the alumite layer is between 90 GPa and 120 GPa. The method also includes a step of forming a particle-resistant layer on the alumite layer by aerosol deposition, in which an aerosol containing fine particles of a brittle material dispersed in a gas is ejected from a nozzle to impact against a surface of the alumite layer, wherein the particle-resistant layer includes a polycrystalline ceramic; and wherein, when the resulting semiconductor manufacturing apparatus member is exposed to a plasma in a reference plasma resistance test, the particle-resistant layer has an arithmetic average height Sa of 0.060 or less after the reference plasma test is completed.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: March 26, 2024
    Assignee: TOTO LTD.
    Inventors: Yasutaka Nitta, Takuma Wada
  • Publication number: 20220139676
    Abstract: A method of making a semiconductor manufacturing apparatus member includes a step of preparing an aluminum base having an alumite layer having a porous columnar structure at an upper surface thereof. The alumite layer is an anodic oxidation film, and a Young's modulus of the alumite layer is between 90 GPa and 120 GPa. The method also includes a step of forming a particle-resistant layer on the alumite layer by aerosol deposition, in which an aerosol containing fine particles of a brittle material dispersed in a gas is ejected from a nozzle to impact against a surface of the alumite layer, wherein the particle-resistant layer includes a polycrystalline ceramic; and wherein, when the resulting semiconductor manufacturing apparatus member is exposed to a plasma in a reference plasma resistance test, the particle-resistant layer has an arithmetic average height Sa of 0.060 or less after the reference plasma test is completed.
    Type: Application
    Filed: November 23, 2021
    Publication date: May 5, 2022
    Inventors: Yasutaka NITTA, Takuma WADA
  • Patent number: 11142829
    Abstract: According to one embodiment, a semiconductor manufacturing apparatus member includes a base and a particle-resistant layer. The base includes a main portion and an alumite layer. The main portion includes aluminum. The alumite layer is provided at a front surface of the main portion. The particle-resistant layer is provided on the alumite layer and includes a polycrystalline ceramic. An Al purity of the main portion is 99.00% or more.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: October 12, 2021
    Assignee: Toto Ltd.
    Inventors: Yasutaka Nitta, Takuma Wada
  • Patent number: 11117356
    Abstract: The composite structure of the present invention includes a substrate, and a structure provided on the substrate surface and having a brittle material as the principal component thereof. The structure is polycrystalline, and the average crystallite size is 100 nm or less. The substrate includes at least a first region containing the substrate surface. The first region includes a filler and a matrix which has a first resin as the principal component thereof. The diameter of 90% of the filler particles (D90) is 1.0-60 ?m, inclusive. The surface area fill rate of the filler at the substrate surface per unit area is greater than 10% and no greater than 70%.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: September 14, 2021
    Assignee: TOTO LTD.
    Inventor: Takuma Wada
  • Patent number: 10759710
    Abstract: Disclosed is provision of a ceramic coat having an excellent low-particle generation as well as a method for assessing the low-particle generation of the ceramic coat. A composite structure including a substrate and a structure which is formed on the substrate and has a surface, wherein the structure includes a polycrystalline ceramic and the composite structure has luminance Sa satisfying a specific value calculated from a TEM image analysis thereof, can be suitably used as an inner member of a semiconductor manufacturing apparatus required to have a low-particle generation.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: September 1, 2020
    Assignee: Toto Ltd.
    Inventors: Junichi Iwasawa, Hiroaki Ashizawa, Takuma Wada, Ryoto Takizawa, Toshihiro Aoshima, Yuuki Takahashi, Atsushi Kinjo
  • Publication number: 20200273675
    Abstract: According to one embodiment, a semiconductor manufacturing apparatus member includes a base and a particle-resistant layer. The base includes a first surface, a second surface crossing the first surface, and an edge portion connecting the first surface and the second surface. The particle-resistant layer includes a polycrystalline ceramic and covering the first surface, the second surface, and the edge portion. The particle-resistant layer includes a first particle-resistant layer provided at the edge portion, and a second particle-resistant layer provided at the first surface. A particle resistance of the first particle-resistant layer is higher than a particle resistance of the second particle-resistant layer.
    Type: Application
    Filed: February 27, 2020
    Publication date: August 27, 2020
    Inventors: Yasutaka NITTA, Takuma WADA, Ryoto TAKIZAWA
  • Publication number: 20200273674
    Abstract: According to one embodiment, a semiconductor manufacturing apparatus member includes a base and a particle-resistant layer. The base includes a main portion and an alumite layer. The main portion includes aluminum. The alumite layer is provided at a front surface of the main portion. The particle-resistant layer is provided on the alumite layer and includes a polycrystalline ceramic. A Young's modulus of the alumite layer is greater than 90 GPa.
    Type: Application
    Filed: February 26, 2020
    Publication date: August 27, 2020
    Inventors: Yasutaka NITTA, Takuma WADA
  • Publication number: 20200270753
    Abstract: According to one embodiment, a semiconductor manufacturing apparatus member includes a base and a particle-resistant layer. The base includes a main portion and an alumite layer. The main portion includes aluminum. The alumite layer is provided at a front surface of the main portion. The particle-resistant layer is provided on the alumite layer and includes a polycrystalline ceramic. An Al purity of the main portion is 99.00% or more.
    Type: Application
    Filed: February 26, 2020
    Publication date: August 27, 2020
    Inventors: Yasutaka NITTA, Takuma WADA
  • Patent number: 10714373
    Abstract: According to one embodiment, an electrostatic chuck includes a ceramic dielectric substrate including a sealing ring provided at a peripheral edge portion of the ceramic dielectric substrate, and an electrode layer including a plurality of electrode components. An outer perimeter of the ceramic dielectric substrate is provided to cause a spacing between the outer perimeter of the ceramic dielectric substrate and an outer perimeter of the electrode layer to be uniform. The spacing between the outer perimeter of the electrode layer and the outer perimeter of the ceramic dielectric substrate is narrower than a spacing of the electrode components. A width of the sealing ring is not less than 0.3 millimeters and not more than 3 millimeters. A width where the electrode layer overlaps the sealing ring is not less than ?0.7 millimeters and not more than 2 millimeters.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: July 14, 2020
    Assignee: Toto Ltd.
    Inventors: Kazuki Anada, Yuichi Yoshii, Takuma Wada
  • Publication number: 20190276368
    Abstract: Disclosed is provision of a ceramic coat having an excellent low-particle generation as well as a method for assessing the low-particle generation of the ceramic coat. A composite structure including a substrate and a structure which is formed on the substrate and has a surface, wherein the structure includes a polycrystalline ceramic and the composite structure has luminance Sa satisfying a specific value calculated from a TEM image analysis thereof, can be suitably used as an inner member of a semiconductor manufacturing apparatus required to have a low-particle generation.
    Type: Application
    Filed: March 8, 2019
    Publication date: September 12, 2019
    Inventors: Junichi IWASAWA, Hiroaki ASHIZAWA, Takuma WADA, Ryoto TAKIZAWA, Toshihiro AOSHIMA, Yuuki TAKAHASHI, Atsushi KINJO
  • Publication number: 20190240961
    Abstract: The composite structure of the present invention includes a substrate, and a structure provided on the substrate surface and having a brittle material as the principal component thereof. The structure is polycrystalline, and the average crystallite size is 100 nm or less. The substrate includes at least a first region containing the substrate surface. The first region includes a filler and a matrix which has a first resin as the principal component thereof. The diameter of 90% of the filler particles (D90) is 1.0-60 ?m, inclusive. The surface area fill rate of the filler at the substrate surface per unit area is greater than 10% and no greater than 70%.
    Type: Application
    Filed: September 14, 2017
    Publication date: August 8, 2019
    Inventor: Takuma Wada
  • Publication number: 20180040499
    Abstract: According to one embodiment, an electrostatic chuck includes a ceramic dielectric substrate including a sealing ring provided at a peripheral edge portion of the ceramic dielectric substrate, and an electrode layer including a plurality of electrode components. An outer perimeter of the ceramic dielectric substrate is provided to cause a spacing between the outer perimeter of the ceramic dielectric substrate and an outer perimeter of the electrode layer to be uniform. The spacing between the outer perimeter of the electrode layer and the outer perimeter of the ceramic dielectric substrate is narrower than a spacing of the electrode components. A width of the sealing ring is not less than 0.3 millimeters and not more than 3 millimeters. A width where the electrode layer overlaps the sealing ring is not less than ?0.7 millimeters and not more than 2 millimeters.
    Type: Application
    Filed: October 19, 2017
    Publication date: February 8, 2018
    Inventors: Kazuki ANADA, Yuichi YOSHII, Takuma WADA
  • Patent number: 9300229
    Abstract: To provide an electrostatic chuck, including: a ceramic dielectric substrate having a first major surface on which an object to be processed is mounted, and a second major surface on a side opposite the first major surface, the ceramic dielectric substrate being a polycrystalline ceramic sintered body; and an electrode layer interposed between the first major surface and the second major surface of the ceramic dielectric substrate, the electrode layer being integrally sintered with the ceramic dielectric substrate, a temperature control plate provided on the second major surface side; and a heater provided between the electrode layer and the temperature control plate, and the first dielectric layer and the second dielectric layer of the ceramic dielectric substrate having an infrared spectral transmittance in terms of a thickness of 1 mm of not less than 20%.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: March 29, 2016
    Assignee: Toto Ltd.
    Inventors: Kazuki Anada, Takuma Wada
  • Patent number: 9252041
    Abstract: To provide an electrostatic chuck, including: a ceramic dielectric substrate having a first major surface on which an object to be processed is mounted, and a second major surface on a side opposite the first major surface, the ceramic dielectric substrate being a polycrystalline ceramic sintered body; and an electrode layer interposed between the first major surface and the second major surface of the ceramic dielectric substrate, the electrode layer being integrally sintered with the ceramic dielectric substrate, and the electrode layer includes a first portion having conductivity, and a second portion that bonds the first dielectric layer and the second dielectric layer, and the mean grain size of crystals included in the second portion is smaller than the mean grain size of crystals included in the ceramic dielectric substrate.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: February 2, 2016
    Assignee: Toto Ltd.
    Inventors: Kazuki Anada, Takuma Wada
  • Patent number: 9252040
    Abstract: To provide an electrostatic chuck, including: a ceramic dielectric substrate having a first major surface on which an object to be processed is mounted, and a second major surface on a side opposite the first major surface, the ceramic dielectric substrate being a polycrystalline ceramic sintered body; and an electrode layer interposed between the first major surface and the second major surface of the ceramic dielectric substrate, the electrode layer being integrally sintered with the ceramic dielectric substrate, the ceramic dielectric substrate including a first dielectric layer between the electrode layer and the first major surface, and a second dielectric layer between the electrode layer and the second major surface, and at least the first dielectric layer of the ceramic dielectric substrate having an infrared spectral transmittance in terms of a thickness of 1 millimeter (mm) of not less than 20%.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: February 2, 2016
    Assignee: Toto Ltd.
    Inventors: Kazuki Anada, Takuma Wada
  • Patent number: 9042078
    Abstract: An electrostatic chuck includes: a ceramic dielectric substrate having a first major surface and a second major surface; an electrode interposed between the first and second major surfaces; and a connecting part connected to the electrode and including a first region in contact with the electrode, with a first direction being defined as a direction from the first major surface toward the second major surface, and a second direction being defined as a direction orthogonal to the first direction, the first region being configured so that in a cross section of the electrode and the connecting part as viewed in the second direction, an angle on a side of the connecting part between an extension line along outer shape on the side of second major surface of the electrode and a tangential line of outer shape of the connecting part gradually increases in the first direction.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: May 26, 2015
    Assignee: Toto Ltd.
    Inventors: Takuma Wada, Kazuki Anada
  • Publication number: 20140355170
    Abstract: An electrostatic chuck includes: a ceramic dielectric substrate having a first major surface and a second major surface; an electrode interposed between the first and second major surfaces; and a connecting part connected to the electrode and including a first region in contact with the electrode, with a first direction being defined as a direction from the first major surface toward the second major surface, and a second direction being defined as a direction orthogonal to the first direction, the first region being configured so that in a cross section of the electrode and the connecting part as viewed in the second direction, an angle on a side of the connecting part between an extension line along outer shape on the side of second major surface of the electrode and a tangential line of outer shape of the connecting part gradually increases in the first direction.
    Type: Application
    Filed: September 27, 2012
    Publication date: December 4, 2014
    Inventors: Takuma Wada, Kazuki Anada
  • Publication number: 20140071582
    Abstract: To provide an electrostatic chuck, including: a ceramic dielectric substrate having a first major surface on which an object to be processed is mounted, and a second major surface on a side opposite the first major surface, the ceramic dielectric substrate being a polycrystalline ceramic sintered body; and an electrode layer interposed between the first major surface and the second major surface of the ceramic dielectric substrate, the electrode layer being integrally sintered with the ceramic dielectric substrate, a temperature control plate provided on the second major surface side; and a heater provided between the electrode layer and the temperature control plate, and the first dielectric layer and the second dielectric layer of the ceramic dielectric substrate having an infrared spectral transmittance in terms of a thickness of 1 mm of not less than 20%.
    Type: Application
    Filed: September 9, 2013
    Publication date: March 13, 2014
    Applicant: TOTO LTD.
    Inventors: Kazuki ANADA, Takuma WADA
  • Publication number: 20140063682
    Abstract: To provide an electrostatic chuck, including: a ceramic dielectric substrate having a first major surface on which an object to be processed is mounted, and a second major surface on a side opposite the first major surface, the ceramic dielectric substrate being a polycrystalline ceramic sintered body; and an electrode layer interposed between the first major surface and the second major surface of the ceramic dielectric substrate, the electrode layer being integrally sintered with the ceramic dielectric substrate, and the electrode layer includes a first portion having conductivity, and a second portion that bonds the first dielectric layer and the second dielectric layer, and the mean grain size of crystals included in the second portion is smaller than the mean grain size of crystals included in the ceramic dielectric substrate.
    Type: Application
    Filed: August 28, 2013
    Publication date: March 6, 2014
    Applicant: TOTO Ltd.
    Inventors: Kazuki ANADA, Takuma WADA
  • Publication number: 20140063681
    Abstract: To provide an electrostatic chuck, including: a ceramic dielectric substrate having a first major surface on which an object to be processed is mounted, and a second major surface on a side opposite the first major surface, the ceramic dielectric substrate being a polycrystalline ceramic sintered body; and an electrode layer interposed between the first major surface and the second major surface of the ceramic dielectric substrate, the electrode layer being integrally sintered with the ceramic dielectric substrate, the ceramic dielectric substrate including a first dielectric layer between the electrode layer and the first major surface, and a second dielectric layer between the electrode layer and the second major surface, and at least the first dielectric layer of the ceramic dielectric substrate having an infrared spectral transmittance in terms of a thickness of 1 millimeter (mm) of not less than 20%.
    Type: Application
    Filed: August 28, 2013
    Publication date: March 6, 2014
    Applicant: TOTO LTD.
    Inventors: Kazuki ANADA, Takuma WADA