Abstract: A vehicle seat, comprising: a seat back pad attached to a seat back frame configuring a frame; a back support device provided on a seat rear side of the seat back pad, configured to assist a seated posture of a seated person, and including an opening penetrating in a seat back thickness direction; and an air conditioning device including an air conditioner configured to suction and blow out air, and a flow path forming portion connected to the air conditioner, inserted into the opening of the back support device, and performing at least one of blowing out air to a side of the seated person or suctioning air from the seated person side in accordance with the air conditioner.

Abstract: A back support device, comprising: a frame portion provided at a seat on which a seated person is seated, the frame portion including a locked portion at an upper portion of the frame portion; an upper frame portion fixed to the upper portion of the frame portion and extending in a seat width direction below the locked portion; a lumbar support portion engaged with a lower portion of the frame portion and configured to support a waist of the seated person from a seat rear side; and a pressure receiving portion including, at an upper end portion thereof, a locking portion locked to the locked portion, the pressure receiving portion being supported by the upper frame portion and the lumbar support portion from the seat rear side, and being configured to be deformable by receiving a load from a back of the seated person.

Abstract: A relay apparatus capable of reducing a load on a private branch exchange when an incoming call is made to an extension representative number is provided. A relay apparatus (1) includes a reception unit (2), a generation unit (4), and a transmission unit (6). The reception unit (2) receives, from the private branch exchange, incoming call notification information indicating an incoming call notification, which is a notification indicating that the incoming call is made to the extension representative number. The generation unit (4) generates a push notification request corresponding to the incoming call notification for each of a plurality of mobile terminals belonging to the group of the extension representative number based on the incoming call notification information. The transmission unit (6) performs processing for transmitting the push notification request to the corresponding mobile terminal.

Abstract: Provided is a taper reamer with which it is possible to achieve an improvement in machining accuracy and machining life. The taper reamer comprises a plurality of cutting edges each having a helical shape provided on the outer periphery of a cutting-edge portion having an external diameter being expanded from a front end toward a rear end thereof, wherein an intertooth angle, defined between each of a pair of the cutting edges adjacently arranged in a circumferential direction, is different from one another at any given reference position, and wherein the plurality of cutting edges each have a helix angle that is different from one another. As the plurality of cutting edges that are unequally partitioned each have the helix angle that is different from one another, a resonance during cutting can be prevented.

Abstract: Provided is a taper reamer with which it is possible to achieve an improvement in machining accuracy and machining life. The taper reamer comprises a plurality of cutting edges each having a helical shape provided on the outer periphery of a cutting-edge portion having an external diameter being expanded from a front end toward a rear end thereof, wherein an intertooth angle, defined between each of a pair of the cutting edges adjacently arranged in a circumferential direction, is different from one another at any given reference position, and wherein the plurality of cutting edges each have a helix angle that is different from one another. As the plurality of cutting edges that are unequally partitioned each have the helix angle that is different from one another, a resonance during cutting can be prevented.

Abstract: A storage system includes a host configured to transmit a write command and store write data in a buffer thereof, and a storage device. The storage device includes a nonvolatile memory including a plurality of blocks, each of the blocks including a plurality of sectors and each of the sectors logically divided into at least a lower page and an upper page for data storage, and a controller configured carry out a write operation to write the write data in the nonvolatile memory in response to the write command, and return a notice to the host acknowledging that the write operation is successful. When a portion of the write data are written in a lower page of a sector of a block and an upper page of the sector remains unwritten after the write operation, the host maintains the portion of the write data in the buffer even after receiving the notice.

Abstract: A storage system includes a host configured to transmit a write command and store write data in a buffer thereof, and a storage device. The storage device includes a nonvolatile memory including a plurality of blocks, each of the blocks including a plurality of sectors and each of the sectors logically divided into at least a lower page and an upper page for data storage, and a controller configured carry out a write operation to write the write data in the nonvolatile memory in response to the write command, and return a notice to the host acknowledging that the write operation is successful. When a portion of the write data are written in a lower page of a sector of a block and an upper page of the sector remains unwritten after the write operation, the host maintains the portion of the write data in the buffer even after receiving the notice.

Abstract: A nonvolatile semiconductor memory device including a memory cell configured to store data and a resistor element provided around the memory cell. The memory cell includes a charge storage layer provided above a substrate, a first semiconductor layer formed on a top surface of the charge storage layer via an insulating layer, and a first low resistive layer formed on a top surface of the first semiconductor layer and having resistance lower than that of the first semiconductor layer. The resistor element includes a second semiconductor layer formed on the same layer as the first semiconductor layer, and a second low resistive layer formed on the same layer as the first low resistive layer and on a top surface of the second semiconductor layer, having resistance lower than that of the second semiconductor layer.

Abstract: A nonvolatile semiconductor memory device including a memory cell configured to store data and a resistor element provided around the memory cell. The memory cell includes a charge storage layer provided above a substrate, a first semiconductor layer formed on a top surface of the charge storage layer via an insulating layer, and a first low resistive layer formed on a top surface of the first semiconductor layer and having resistance lower than that of the first semiconductor layer. The resistor element includes a second semiconductor layer formed on the same layer as the first semiconductor layer, and a second low resistive layer formed on the same layer as the first low resistive layer and on a top surface of the second semiconductor layer, having resistance lower than that of the second semiconductor layer.

Abstract: A nonvolatile semiconductor memory device comprises a memory cell configured to store data and a resistor element provided around the memory cell. The memory cell includes a charge storage layer provided above a substrate, a first semiconductor layer formed on a top surface of the charge storage layer via an insulating layer, and a first low resistive layer formed on a top surface of the first semiconductor layer and having resistance lower than that of the first semiconductor layer. The resistor element includes a second semiconductor layer formed on the same layer as the first semiconductor layer, and a second low resistive layer formed on the same layer as the first low resistive layer and on a top surface of the second semiconductor layer, having resistance lower than that of the second semiconductor layer.

Abstract: A semiconductor memory device includes a sense amplifier which senses identical multilevel data, which is stored in a memory cell, a plurality of number of times at a time of read, and a n-channel MOS transistor which has a current path one end of which is connected to the sense amplifier and the other end of which is connected to a bit line. The device further include a control unit which applies a first voltage to a gate electrode of the n-channel MOS transistor, thereby setting the n-channel MOS transistor in an ON state, and applies a second voltage which is higher than the first voltage, to the gate electrode during a period after first sense and before second sense.

Abstract: The nonvolatile semiconductor memory device related to an embodiment of the present invention includes a cell array including a memory string, a bit line connected to the memory string, a first wire connected to a cell source line of a memory cell, a second wire connected to a cell well line of a memory cell, a third wire which supplies a power supply voltage to a circuit arranged outside of a region of the cell array, a fourth wire and a fifth wire being arranged in a row direction within the cell array region, and the first wire, the second wire and the third being formed in a layer above a layer in which the bit line within the cell array is formed, the fourth wire and the fifth wire being formed in the layer in which the bit line within the cell array region is formed.

Abstract: A semiconductor memory device includes a plurality of memory cells, signal lines, and a control unit. Each of the plurality of memory cells includes a charge storage layer. Each of the plurality of memory cells includes a control gate and is configured to hold two-or-higher-level data. Each of signal lines is electrically connected with a gate or one end of a current path of each of the memory cells. Each of signal lines has a line width which differs depending on each interval between the memory cells adjacent to each other. The control unit controls a voltage applied to each of the signal lines in accordance with the line width of each of the signal lines.

Abstract: A semiconductor memory device includes a sense amplifier which senses identical multilevel data, which is stored in a memory cell, a plurality of number of times at a time of read, and a n-channel MOS transistor which has a current path one end of which is connected to the sense amplifier and the other end of which is connected to a bit line. The device further include a control unit which applies a first voltage to a gate electrode of the n-channel MOS transistor, thereby setting the n-channel MOS transistor in an ON state, and applies a second voltage which is higher than the first voltage, to the gate electrode during a period after first sense and before second sense.

Abstract: A semiconductor memory device according to an embodiment of the present invention includes a resistance element which is constructed with a first conductor which extends in a first direction and is connected to a first contact; a second conductor which extends in said first direction and is connected to a second contact; and a first insulation film which exists between said first conductor and said second conductor, said first insulation film also having an opening in which a third conductor which connects said first conductor and said second conductor is arranged.

Abstract: A non-volatile semiconductor memory device includes a memory cell array having a plurality of non-volatile memory cells capable electrically rewriting data, bit lines and source lines. A driver circuit is coupled with the source lines of the memory cell array to output a voltage higher than a power source voltage or a programming voltage for writing data in the memory cell by switching over, and the driver circuit discharges the source lines to ground. A sense amplifier circuit is coupled with the bit line and reads out the data in the memory cell. The sense amplifier includes a sense node and a capacitor having first and second terminals, and the first terminal is coupled with the sense node. The sense node is boosted by a plurality of voltages applied to the second terminal of the capacitor.

Abstract: A semiconductor memory device includes a sense amplifier which senses identical multilevel data, which is stored in a memory cell, a plurality of number of times at a time of read, and a n-channel MOS transistor which has a current path one end of which is connected to the sense amplifier and the other end of which is connected to a bit line. The device further include a control unit which applies a first voltage to a gate electrode of the n-channel MOS transistor, thereby setting the n-channel MOS transistor in an ON state, and applies a second voltage which is higher than the first voltage, to the gate electrode during a period after first sense and before second sense.

Abstract: A nonvolatile semiconductor memory device comprises a memory cell configured to store data and a resistor element provided around the memory cell. The memory cell includes a charge storage layer provided above a substrate, a first semiconductor layer formed on a top surface of the charge storage layer via an insulating layer, and a first low resistive layer formed on a top surface of the first semiconductor layer and having resistance lower than that of the first semiconductor layer. The resistor element includes a second semiconductor layer formed on the same layer as the first semiconductor layer, and a second low resistive layer formed on the same layer as the first low resistive layer and on a top surface of the second semiconductor layer, having resistance lower than that of the second semiconductor layer. The second semiconductor layer is formed to extend in a first direction parallel to the substrate.

Abstract: A semiconductor memory device includes a plurality of memory cells, signal lines, and a control unit. Each of the plurality of memory cells includes a charge storage layer. Each of the plurality of memory cells includes a control gate and is configured to hold two-or-higher-level data. Each of signal lines is electrically connected with a gate or one end of a current path of each of the memory cells. Each of signal lines has a line width which differs depending on each interval between the memory cells adjacent to each other. The control unit controls a voltage applied to each of the signal lines in accordance with the line width of each of the signal lines.

Abstract: A semiconductor memory device includes a sense amplifier which senses identical multilevel data, which is stored in a memory cell, a plurality of number of times at a time of read, and a n-channel MOS transistor which has a current path one end of which is connected to the sense amplifier and the other end of which is connected to a bit line. The device further include a control unit which applies a first voltage to a gate electrode of the n-channel MOS transistor, thereby setting the n-channel MOS transistor in an ON state, and applies a second voltage which is higher than the first voltage, to the gate electrode during a period after first sense and before second sense.