Abstract: A reverse conduction loss reduction circuit operates, when an enhancement-mode switching element having reverse conduction characteristics corresponding to a gate-source voltage is reverse-conducting, to raise the gate-source voltage of the switching element to a predetermined bias voltage.

Abstract: A driving circuit is configured to be capable of driving a switching element. The driving circuit obtains temperature information of the switching element, and changes driving capability of the switching element based on the temperature information, in at least one of turning on and turning off the switching element.

Abstract: The present disclosure provides a power factor improvement circuit with a DC/DC converter including an arithmetic circuit. A first voltage having a full-wave rectified waveform is received by an input voltage detection terminal of the power factor improvement circuit. A second voltage is generated by amplifying an error between a first detection voltage and a reference voltage according to an output voltage of the DC/DC converter. A third voltage is generated by multiplying the first voltage by the second voltage. The arithmetic circuit adds an offset voltage to a third voltage to generate a fourth voltage. A comparator is configured to compare a second detection voltage with the fourth voltage. A drive circuit is configured to turn on/off drive of the switching transistor according to an output of the comparator. When the second detection voltage is higher than the fourth voltage, the switching transistor is turned off.

Abstract: The present disclosure provides a power factor improvement circuit with a DC/DC converter including an arithmetic circuit. A first voltage having a full-wave rectified waveform is received by an input voltage detection terminal of the power factor improvement circuit. A second voltage is generated by amplifying an error between a first detection voltage and a reference voltage according to an output voltage of the DC/DC converter. A third voltage is generated by multiplying the first voltage by the second voltage. The arithmetic circuit adds an offset voltage to a third voltage to generate a fourth voltage. A comparator is configured to compare a second detection voltage with the fourth voltage. A drive circuit is configured to turn on/off drive of the switching transistor according to an output of the comparator. When the second detection voltage is higher than the fourth voltage, the switching transistor is turned off.

Abstract: The present disclosure provides a power factor improvement circuit with a DC/DC converter including an arithmetic circuit. A first voltage having a full-wave rectified waveform is received by an input voltage detection terminal of the power factor improvement circuit. A second voltage is generated by amplifying an error between a first detection voltage and a reference voltage according to an output voltage of the DC/DC converter. A third voltage is generated by multiplying the first voltage by the second voltage. The arithmetic circuit adds an offset voltage to a third voltage to generate a fourth voltage. A comparator is configured to compare a second detection voltage with the fourth voltage. A drive circuit is configured to turn on/off drive of the switching transistor according to an output of the comparator.