Abstract: A fault simulation method for simulating an entire circuit represented by a gate model, comprises the steps of preparing a plurality of fault circuits represented by gate models, which are equal in number to the number of internal faults, with the internal faults assumed in the entire circuit, of dividing each of the fault circuits into a plurality of partial circuits each of which is represented by the gate model, of replacing internal faults in the partial circuits with external faults out of the partial circuits that are equivalent to the internal faults; of translating the partial circuits into translated partial circuits represented by superior models which have operation speed faster than that of the gate models, and of simultaneously simulating both of a good circuit represented by the superior model and the fault circuits represented by the superior models to determine whether or not the internal faults can be detected by comparing results of simulations.