Patents by Inventor Takumi Kawai
Takumi Kawai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7075159Abstract: This invention provides a horizontal MOS transistor capable of improving current drivability and reducing ON resistance by optimizing the gate wiring structure and the disposition structure of source/drain layers. First gate wirings are disposed in the X direction at a pitch Y1 in the Y direction and second gate wirings 12 are disposed in the Y direction with two pieces as a pair such that they meander at a pitch X1 in the X direction. The meandering of the second gate wiring 12 is formed so as to sandwich the bent portions 14 substantially in the center of the pitch Y1. A bottle-like shape diffusion layer region in which the wide-width region and narrow-width region are combined is sectioned by adjacent first and second wirings. A contact 16 for connecting the diffusion layer region to the wiring layer 18 is disposed in the wide-width region and wiring layers 18 are disposed such that two rows run in parallel in the X direction.Type: GrantFiled: August 5, 2004Date of Patent: July 11, 2006Assignee: Fujitsu LimitedInventors: Shinichiro Suga, Takumi Kawai
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Publication number: 20050212012Abstract: This invention provides a horizontal MOS transistor capable of improving current drivability and reducing ON resistance by optimizing the gate wiring structure and the disposition structure of source/drain layers. First gate wirings are disposed in the X direction at a pitch Y1 in the Y direction and second gate wirings 12 are disposed in the Y direction with two pieces as a pair such that they meander at a pitch X1 in the X direction. The meandering of the second gate wiring 12 is formed so as to sandwich the bent portions 14 substantially in the center of the pitch Y1. A bottle-like shape diffusion layer region in which the wide-width region and narrow-width region are combined is sectioned by adjacent first and second wirings. A contact 16 for connecting the diffusion layer region to the wiring layer 18 is disposed in the wide-width region and wiring layers 18 are disposed such that two rows run in parallel in the X direction.Type: ApplicationFiled: August 5, 2004Publication date: September 29, 2005Applicant: FUJITSU LIMITEDInventors: Shinichiro Suga, Takumi Kawai
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Patent number: 6522491Abstract: A magnetoresistive element input circuit includes a first resistor connected between a magnetoresistive (MR) element and a first power source. A first current source is connected between the MR element and a second power source and supplies a DC bias current to the MR element in an active mode. A second resistor is connected between the MR element and the first current source. A capacitor is connected to a node between the second resistor and the first current source and to the first power supply. A differential amplifier is connected to the MR element. A voltage supply circuit is connected to the node and supplies the node with a voltage, when the input circuit is in an inactive mode, which is substantially equal to the voltage supplied to the node when the input circuit is in the active mode.Type: GrantFiled: July 25, 2000Date of Patent: February 18, 2003Assignee: Fujitsu LimitedInventor: Takumi Kawai
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Patent number: 6466080Abstract: A constant-current driver circuit for on-off controlling an output current at a high speed is provided. The constant-current driver circuit includes a first MOS transistor to which a reference current is provided and a second MOS transistor connected to the first MOS transistor for generating an output current having a predetermined ratio to the reference current. A switch circuit is connected to the second MOS transistor to on-off control the output current in accordance with the input signal. A bias circuit is connected to the gate of the second MOS transistor to provide a bias voltage to the gate of the second MOS transistor so that variation in the gate voltage of the second MOS transistor is suppressed.Type: GrantFiled: March 23, 2001Date of Patent: October 15, 2002Assignee: Fujitsu LimitedInventors: Takumi Kawai, Akihiko Ono
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Publication number: 20020044008Abstract: A constant-current driver circuit for on-off controlling an output current at a high speed is provided. The constant-current driver circuit includes a first MOS transistor to which a reference current is provided and a second MOS transistor connected to the first MOS transistor for generating an output current having a predetermined ratio to the reference current. A switch circuit is connected to the second MOS transistor to on-off control the output current in accordance with the input signal. A bias circuit is connected to the gate of the second MOS transistor to provide a bias voltage to the gate of the second MOS transistor so that variation in the gate voltage of the second MOS transistor is suppressed.Type: ApplicationFiled: March 23, 2001Publication date: April 18, 2002Inventors: Takumi Kawai, Akihiko Ono
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Patent number: 6255898Abstract: A noise eliminating circuit eliminates thermal asperity noise in a reproduction signal generated by a magnetic read head in a disk drive. The noise eliminating circuit includes a differential amplifier that receives the reproduction signal and a feedback signal and generates an amplified signal. A detection circuit connected to the differential amplifier detects noise in the amplified signal and generates a control signal. The control signal is activated when the noise is detected. A feedback circuit connected to the differential amplifier and the detection circuit cuts off the amplified signal with a first cutoff frequency when the control signal is not active and cuts off the amplified signal with a second cutoff frequency when the control signal is active.Type: GrantFiled: June 22, 2000Date of Patent: July 3, 2001Assignee: Fujitsu LimitedInventors: Akihiko Ono, Takumi Kawai
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Patent number: 5452148Abstract: A preamplifying circuit to amplify signals detected by a magnetoresistance device for a magnetic head. Two terminals of the magnetoresistance device are connected via a first resistor to a power source line Vcc and via a second resistor to a current input terminal of a constant current source having an output terminal which is connected to a ground line, respectively. A first capacitor is connected between the power source line Vcc and an input terminal of the constant current source. The two terminals of the magnetoresistance device are connected to bases of first and second transistors, respectively, in a differential amplification circuit. With this, because the input impedances at both terminals of the magnetoresistance device are equal, the external noise added to both of the terminals of the magnetoresistance device via parasitic capacitance become inphase.Type: GrantFiled: February 22, 1994Date of Patent: September 19, 1995Assignee: Fujitsu LimitedInventors: Takumi Kawai, Chikara Tsuchiya
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Patent number: 5214913Abstract: A method of and apparatus for controlling a triple-coil servo valve arranged having a tripled control system each of which is composed of components of a coil, a servo amplifier and a controller, the method of and the apparatus for controlling the triple servo valve including means for specifying the abnormality of each of the components, servo amplifier output separation means, means capable of desirably combining the components and means for compensating the servo amplifier. If two control systems of the tripled control system are faulty in such a manner that at least one coil, at least one servo amplifier or at least one controller is abnormal, the triple-coil servo is operated by combining the normal components or by compensating the servo amplifier so that the continuation of the operation of the plant is enabled.Type: GrantFiled: May 22, 1991Date of Patent: June 1, 1993Assignee: Hitachi, Ltd.Inventors: Yukiyoshi Tani, Sadao Yanada, Takeshi Iwamiya, Takumi Kawai, Tadahiko Iijima
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Patent number: 4825352Abstract: A process control system has a timer circuit which fixes operational periods by issuing an instruction for starting each of a plurality of time periods in such a manner that the computation of control blocks will occur during periods of fixed duration. A periodic operation selection circuit selects control blocks to be computed within each time period in response to an instruction from the timer circuit. Control blocks selected by the periodic operation selection circuit and an instruction for completion of the computation of control blocks for each time period are stacked in an operation instruction circuit, which issues an instruction for consecutively executing the operation of the control blocks and an instruction for effecting an idle operation after completion of the operation of control blocks for each time period.Type: GrantFiled: March 23, 1987Date of Patent: April 25, 1989Assignee: Hitachi, Ltd.Inventors: Tadahiko Iijima, Takumi Kawai, Yasuhiro Tennichi, Sadao Yanada