Patents by Inventor Takumi Mikawa

Takumi Mikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11889776
    Abstract: A variable resistance non-volatile memory element includes first and second electrodes and a variable resistance layer between the electrodes. The layer has a resistance value reversibly variable based on an electrical signal. The layer includes a first variable resistance layer that includes an oxygen deficient first metal oxide containing a first metal element and oxygen, and a second variable resistance layer that includes a composite oxide containing the first metal element, a second metal element different from the first metal element, and oxygen, and having a different degree of oxygen deficiency from the first metal oxide. The composite oxide has a lower degree of oxygen deficiency than the first metal oxide. At room temperature, the composite oxide has a smaller oxygen diffusion coefficient than a second metal oxide containing the first metal element and oxygen, and having the degree of oxygen deficiency equal to that of the composite oxide.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: January 30, 2024
    Assignee: Nuvoton Technology Corporation Japan
    Inventors: Ryutaro Yasuhara, Satoru Fujii, Takumi Mikawa, Atsushi Himeno, Kengo Nishio, Takehide Miyazaki, Hiroyuki Akinaga, Yasuhisa Naitoh, Hisashi Shima
  • Publication number: 20220198251
    Abstract: A semiconductor device includes variable resistance elements on a semiconductor substrate. Each of the variable resistance elements includes a first electrode, a second electrode, and a variable resistance layer that is sandwiched between the first electrode and the second electrode and that stores a resistance value that is continuously variable. The variable resistance layer includes a filament whose shape differs according to a neural network weight, and stores, as an analog value, the resistance value that is variable.
    Type: Application
    Filed: March 10, 2022
    Publication date: June 23, 2022
    Inventors: Takumi MIKAWA, Koji KATAYAMA, Ryutaro YASUHARA
  • Publication number: 20210320248
    Abstract: A variable resistance non-volatile memory element includes first and second electrodes and a variable resistance layer between the electrodes. The layer has a resistance value reversibly variable based on an electrical signal. The layer includes a first variable resistance layer that includes an oxygen deficient first metal oxide containing a first metal element and oxygen, and a second variable resistance layer that includes a composite oxide containing the first metal element, a second metal element different from the first metal element, and oxygen, and having a different degree of oxygen deficiency from the first metal oxide. The composite oxide has a lower degree of oxygen deficiency than the first metal oxide. At room temperature, the composite oxide has a smaller oxygen diffusion coefficient than a second metal oxide containing the first metal element and oxygen, and having the degree of oxygen deficiency equal to that of the composite oxide.
    Type: Application
    Filed: June 23, 2021
    Publication date: October 14, 2021
    Inventors: Ryutaro YASUHARA, Satoru FUJII, Takumi MIKAWA, Atsushi HIMENO, Kengo NISHIO, Takehide MIYAZAKI, Hiroyuki AKINAGA, Yasuhisa NAITOH, Hisashi SHIMA
  • Patent number: 9680093
    Abstract: A nonvolatile memory element including: a first electrode; a second electrode; a variable resistance layer that is between the first electrode and the second electrode and includes, as stacked layers, a first variable resistance layer connected to the first electrode and a second variable resistance layer connected to the second electrode; and a side wall protecting layer that has oxygen barrier properties and covers a side surface of the variable resistance layer. The first variable resistance layer includes a first metal oxide and a third metal oxide formed around the first metal oxide and having an oxygen deficiency lower than that of the first metal oxide, and the second variable resistance layer includes a second metal oxide having an oxygen deficiency lower than that of the first metal oxide.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: June 13, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shinichi Yoneda, Takumi Mikawa, Satoru Ito, Yukio Hayakawa, Atsushi Himeno
  • Patent number: 9595563
    Abstract: A nonvolatile memory device includes: a pair of first wirings extending in a first direction; a second wiring extending in a second direction crossing the first direction; a pair of third wirings extending in the second direction; and a fourth wiring located between the pair of the third wirings. The nonvolatile memory device has four resistance-change elements each which is provided adjacent to respective four crossing areas in which each of the pair of first wirings intersects with each of the pair of third wirings, and a first contact plug disposed at an intersection of two diagonals of a virtual tetragon defined by the four resistance-change elements. Two transistors arranged in the second direction, among four transistors, share each one first main terminal located between the pair of the first wirings, the shared each one first main terminal being connected to the second wiring.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: March 14, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Satoru Ito, Takumi Mikawa, Kazuhiko Shimakawa
  • Patent number: 9570682
    Abstract: Provided are a variable resistance semiconductor memory device which changes its resistance without being affected by an underlying layer and is suitable as a memory device of increased capacity, and a method of manufacturing the same. The semiconductor memory device in the present invention includes: a first contact plug formed inside a first contact hole penetrating through a first interlayer insulating layer; a lower electrode having a flat top surface and is thicker above the first interlayer insulating layer than above the first contact plug; a variable resistance layer; and an upper electrode. The lower electrode, the variable resistance layer, and the upper electrode compose a variable resistance element.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: February 14, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takumi Mikawa, Takashi Okada
  • Publication number: 20160035976
    Abstract: Provided are a variable resistance semiconductor memory device which changes its resistance without being affected by an underlying layer and is suitable as a memory device of increased capacity, and a method of manufacturing the same. The semiconductor memory device in the present invention includes: a first contact plug formed inside a first contact hole penetrating through a first interlayer insulating layer; a lower electrode having a flat top surface and is thicker above the first interlayer insulating layer than above the first contact plug; a variable resistance layer; and an upper electrode. The lower electrode, the variable resistance layer, and the upper electrode compose a variable resistance element.
    Type: Application
    Filed: October 9, 2015
    Publication date: February 4, 2016
    Inventors: Takumi MIKAWA, Takashi OKADA
  • Patent number: 9252189
    Abstract: A nonvolatile semiconductor memory element includes: a variable resistance element including a first electrode, a variable resistance layer, and a second electrode, and having a resistance value which changes according to a polarity of an electric pulse applied between the first electrode and the second electrode; and a current steering element which is electrically connected to the variable resistance element, allows a current to flow bidirectionally, and has a nonlinear current-voltage characteristic. The current steering element (i) has a structure in which a first current steering element electrode, a first current steering layer, and a second current steering element electrode are stacked in this order, and (ii) includes a second current steering layer which covers side surfaces of the first current steering element electrode, the first current steering layer, and the second current steering element electrode.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: February 2, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Satoru Fujii, Kiyotaka Tsuji, Takumi Mikawa
  • Patent number: 9214628
    Abstract: A nonvolatile memory element according to the present invention includes a first metal line; a plug formed on the first metal line and connected to the first metal line; a stacked structure including a first electrode, a second electrode, and a variable resistance layer, the stacked structure being formed on a plug which is connected to the first electrode; a second metal line formed on the stacked structure and directly connected to the second electrode; and a side wall protective layer which covers the side wall of the stacked structure and has an insulating property and an oxygen barrier property, wherein part of a lower surface of the second metal line is located under an upper surface of the stacked structure.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: December 15, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Atsushi Himeno, Haruyuki Sorada, Yukio Hayakawa, Takumi Mikawa
  • Patent number: 9184381
    Abstract: A variable resistance nonvolatile storage element includes: a first electrode; a second electrode; and a variable resistance layer having a resistance value that reversibly changes based on an electrical signal applied between the electrodes, wherein the variable resistance layer has a structure formed by stacking a first transition metal oxide layer, a second transition metal oxide layer, and a third transition metal oxide layer in this order, the first transition metal oxide layer having a composition expressed as MOx (where M is a transition metal and O is oxygen), the second transition metal oxide layer having a composition expressed as MOy (where x>y), and the third transition metal oxide layer having a composition expressed as MOz (where y>z).
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: November 10, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takumi Mikawa, Yukio Hayakawa, Takeki Ninomiya, Yoshio Kawashima, Shinichi Yoneda
  • Patent number: 9172038
    Abstract: A variable resistance layer between a first electrode and a second electrode includes: a first variable resistance layer contacting the first electrode; and a second variable resistance layer contacting the second electrode and having a lower degree of oxygen deficiency than the first variable resistance layer. A principal face of the first variable resistance layer which is close to the second variable resistance layer is flat. The second variable resistance layer is in contact with both the first variable resistance layer and the second electrode in a polygonal region including a vertex inward of an outline of the variable resistance layer and vertices along the outline when seen from a direction perpendicular to the principal face of the variable resistance layer, and is not in contact with at least one of the first variable resistance layer and the second electrode in a region outside the region inside the polygon.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: October 27, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yukio Hayakawa, Takumi Mikawa
  • Publication number: 20150295012
    Abstract: A nonvolatile memory device includes: a pair of first wirings extending in a first direction; a second wiring extending in a second direction crossing the first direction; a pair of third wirings extending in the second direction; and a fourth wiring located between the pair of the third wirings. The nonvolatile memory device has four resistance-change elements each which is provided adjacent to respective four crossing areas in which each of the pair of first wirings intersects with each of the pair of third wirings, and a first contact plug disposed at an intersection of two diagonals of a virtual tetragon defined by the four resistance-change elements. Two transistors arranged in the second direction, among four transistors, share each one first main terminal located between the pair of the first wirings, the shared each one first main terminal being connected to the second wiring.
    Type: Application
    Filed: April 3, 2015
    Publication date: October 15, 2015
    Inventors: SATORU ITO, TAKUMI MIKAWA, KAZUHIKO SHIMAKAWA
  • Patent number: 9142775
    Abstract: A method of manufacturing a semiconductor device according to the present invention includes: forming a lower electrode above a substrate; forming, above the lower electrode, a first variable resistance layer comprising a first metal oxide; forming a step region in the first variable resistance layer by collision of ions excited by plasma; removing residue of the first variable resistance layer created in the forming of the step region; forming a second variable resistance layer which covers the step region of the first variable resistance layer, comprises a second metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first metal oxide, and has a bend on a step formed along an edge of the step region; and forming an upper electrode above the second variable resistance layer.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: September 22, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yukio Hayakawa, Atsushi Himeno, Hideaki Murase, Yoshio Kawashima, Takumi Mikawa
  • Patent number: 9130167
    Abstract: A method of manufacturing a nonvolatile memory device includes: forming a first electrode; forming, above the first electrode, a metal oxide material layer including a first metal oxide; forming a mask above part of the metal oxide material layer main surface; forming, in a region of the metal oxide material layer not covered by the mask, a high oxygen concentration region including a second metal oxide having a lower degree of oxygen deficiency than the first metal oxide; removing the mask; forming, above a first variable resistance layer including the high oxygen concentration region and a low oxygen concentration region that is a region of the metal oxide material layer other than the high oxygen concentration region, a second variable resistance layer including a third metal oxide having a lower degree of oxygen deficiency than the first metal oxide; and forming a second electrode above the second variable resistance layer.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: September 8, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hideaki Murase, Yoshio Kawashima, Atsushi Himeno, Takumi Mikawa
  • Patent number: 9105332
    Abstract: Provided is a variable resistance element (Rij) the resistance state of which is reversibly changed by applying electrical signals of different polarities; and a current steering element (Dij) in which a first current is larger than a second current, the first current being a current which flows when a voltage of the first polarity having a first value is applied, the first value being less than a predetermined voltage value and having an absolute value greater than zero, the second current being a current which flows when a voltage of the second polarity having an absolute value which is the first value is applied, the second polarity being different from the first polarity, in which Rij and Dij are connected in series such that the polarity of a voltage to be applied to Dij is the second polarity when the resistance state of Rij is changed to high resistance state.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: August 11, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yuichiro Ikeda, Kazuhiko Shimakawa, Koji Katayama, Takumi Mikawa, Kiyotaka Tsuji
  • Patent number: 9082974
    Abstract: A nonvolatile memory element includes: a lower electrode formed above a substrate; a first variable resistance layer formed above the lower electrode and comprising a first metal oxide; a second variable resistance layer formed above the first variable resistance layer and comprising a second metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first metal oxide; and an upper electrode formed above the second variable resistance layer. A single step is formed in an interface between the first variable resistance layer and the second variable resistance layer. The second variable resistance layer is formed to cover the step and have, above the step, a bend (or stepped portion) covering the step. The bend, seen from above, has only one corner in a surface of the second variable resistance layer.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: July 14, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Takumi Mikawa, Hideaki Murase
  • Patent number: 9082971
    Abstract: A variable resistance layer includes a first variable resistance layer comprising a first metal oxide that is oxygen deficient and a second variable resistance layer comprising a second metal oxide having a degree of oxygen deficiency that is different from that of the first metal oxide, wherein the second variable resistance layer includes a non-metal element A that is different from oxygen, x<(y+z) is satisfied where a composition of the first variable resistance layer is represented by MOx and a composition of the second variable resistance layer is represented by NOyAz, the second variable resistance layer has a higher resistivity than a resistivity of the first variable resistance layer, and a film density of the second variable resistance layer is lower than a theoretical film density of the second metal oxide which has a stoichiometric composition.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: July 14, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Satoru Fujii, Takumi Mikawa
  • Patent number: 9082968
    Abstract: In a method of manufacturing a variable resistance non-volatile memory device including non-volatile memory element layers stacked together by repeating the step (S100, S200 . . .
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: July 14, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takumi Mikawa, Shinichi Yoneda
  • Patent number: 9076959
    Abstract: A method of manufacturing a non-volatile memory device comprises: forming a first electrode layer; a variable resistance material layer, a second electrode layer; and a hard mask layer, forming a first resist mask extending in a first direction on the hard mask layer; forming a first hard mask extending in the first direction by etching the hard mask layer using the first resist mask; forming a second resist mask extending in a second direction, on the first hard mask such that the width of the second resist mask is greater than the width of the first resist mask; forming a second hard mask by etching the first hard mask using the second resist mask; and forming a variable resistance element by patterning, by etching the second electrode layer, the variable resistance material layer and the first electrode layer using the second hard mask.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: July 7, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hideaki Murase, Satoru Ito, Yoshio Kawashima, Takumi Mikawa
  • Publication number: 20150171324
    Abstract: A method of manufacturing a variable resistance nonvolatile memory device includes: forming, above a substrate, a metal-semiconductor-metal (MSM) diode element; forming a variable resistance element on the MSM diode element; forming a first oxygen barrier layer which covers a side wall of a semiconductor layer of the MSM diode element, and does not cover at least part of a side wall of a variable resistance layer of the variable resistance element; and oxidizing the side wall of the variable resistance layer which is exposed without being covered by the first oxygen barrier layer.
    Type: Application
    Filed: January 10, 2013
    Publication date: June 18, 2015
    Applicant: Panasonic Corporation
    Inventors: Takumi Mikawa, Atsushi Himeno, Hideaki Murase