Abstract: A three-dimensional memory device includes a pair of alternating stacks of insulating layers and electrically conductive layers, where the pair of alternating stacks are laterally spaced from each other by a lateral isolation trench, memory openings vertically extending through a respective alternating stack of the pair of alternating stacks, memory opening fill structures located in a respective one of the memory openings and including a respective vertical semiconductor channel and a respective vertical stack of memory elements, and a lateral isolation trench fill structure located in the lateral isolation trench. Phosphorus-doped silicon oxide portions are located within or on sidewalls of the lateral isolation trench at levels of the insulating layers.

Abstract: A memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, a source layer overlying the first-tier alternating stack, a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the source layer, a memory opening vertically extending through the first-tier alternating stack, the source layer, and the second-tier alternating stack, a memory opening fill structure located in the memory opening and comprising a vertical stack of first memory elements and a vertical semiconductor channel vertically extending through each of the first electrically conductive layers, the source layer, and the second electrically conductive layers, and having a sidewall in contact with the source layer, and a bottom drain region in contact with a bottom portion of the vertical semiconductor channel.

Abstract: A method of making a memory device includes forming an alternating stack of insulating layers and sacrificial material layers, where a silicon oxycarbide liner is interposed between a first sacrificial material layer and a first insulating layer, and the first sacrificial material layer is direct contact with a second insulating layer or a dielectric material layer composed of a silicon oxide material, forming a memory opening through the alternating stack, forming a memory opening fill structure in the memory opening, forming backside recesses by removing the sacrificial material layers selective to the silicon oxycarbide liner, and forming electrically conductive layers in the backside recesses.

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, such that a first electrically conductive layer of the electrically conductive layers is in contact with an underlying silicon oxycarbide liner and with an overlying silicon oxycarbide liner, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory film containing a continuous memory material layer which continuously extends through the entire alternating stack.

Abstract: Memory stack structures including electrically floating vertical semiconductor channels can vertically extend through an alternating stack of insulating layers and electrically conductive layers. Metal interconnect structures connected to the electrically floating vertical semiconductor channels can be temporarily electrically grounded by a connection via structure that contacts a semiconducting or conductive carrier substrate, which is subsequently removed. The conductive via structure may be formed through the alternating stack, through a vertical stack of dielectric material plates and the insulating layers, or through a dielectric material portion. The conductive via structure may be connected to at least one bit line. In case the conductive via structure is temporarily connected to a plurality bit lines, the conductive via structure can be subsequently isolated from the bit lines.

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, and comprising stepped surfaces, a memory opening vertically extending through each layer within the alternating stack, a memory opening fill structure located in the memory opening and including a vertical stack of memory elements and a vertical semiconductor channel, a dielectric material layer that extends from a bottommost vertical step of the stepped surfaces to a topmost vertical step of the stepped surfaces, and a contact via structure including an upper contact via portion having an annular bottom surface that contacts an annular top surface of a first electrically conductive layer of the electrically conductive layers, and a lower contact via portion that vertically extends through a first subset of the electrically conductive layers that underlie the first electrically conductive layer, and the lower contact via portion is narrower than the upper contact via portion.

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. A plurality of arrays of memory opening fill structures is formed through the alternating stack. A plurality of dielectric plates is formed, which laterally surrounds a respective array of memory opening fill structures. Self-aligned drain-select-level isolation structures are formed between a respective neighboring pair of arrays of memory opening fill structures through gaps between neighboring pairs of the dielectric plates into a subset of layers within the alternating stack. Drain side select gate electrodes are provided from a divided subset of the spacer material layers.

Abstract: A method of forming a memory device includes forming an insulating layer and a composite sacrificial material layer having a vertical compositional change that is stepwise or gradual such that a bottommost portion and a topmost portion of the composite sacrificial material layer a different etch rate in an isotropic etchant than the middle portion, forming a memory opening, laterally recessing the composite sacrificial material layers selective to the insulating layers around the memory opening by introducing the isotropic etchant into the memory opening to form lateral recesses in the composite sacrificial material layers, forming a memory opening fill structure within the memory opening, where the memory opening fill structure includes a vertical stack of memory elements that are formed in the lateral recesses, a dielectric material liner, and a vertical semiconductor channel, and replacing the composite sacrificial material layers with electrically conductive layers.

Abstract: A protection circuit protects a rectifier circuit from an inrush current inputted to a smoothing circuit. A short-circuiting circuit does not short the protection circuit while an inrush current may occur, and shorts it while an inrush current does not occur. A transformer has a primary winding, a secondary winding and an auxiliary winding. A delay circuit delays a timing at which an operation of a load connected to the auxiliary winding is started with respect to a timing at which an operation of the short-circuiting circuit is started. A rectifying and smoothing circuit generates an output voltage by rectifying and smoothing the secondary side voltage. The short-circuiting circuit is driven by the output voltage.

Abstract: A power source apparatus includes a plurality of first power sources, each connected to a load through a power supply line, and at least one second power source, which is a sub power source to be used when the first power source is unable to output a predetermined voltage. The second power source is connected in parallel to the power supply line of at least one of the first power source through a diode. The second power source is provided on an anode side of the diode, the load is configured to operate at a voltage equal to or more than a first voltage, the first power source outputs a second voltage higher than the first voltage, the second power source outputs a third voltage, which is higher than the first voltage, the voltage output through the diode from the second power source being lower than the second voltage.

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. A plurality of arrays of memory opening fill structures is formed through the alternating stack. A plurality of dielectric plates is formed, which laterally surrounds a respective array of memory opening fill structures. Self-aligned drain-select-level isolation structures are formed between a respective neighboring pair of arrays of memory opening fill structures through gaps between neighboring pairs of the dielectric plates into a subset of layers within the alternating stack. Drain side select gate electrodes are provided from a divided subset of the spacer material layers.

Abstract: An image forming apparatus is provided that includes an image forming unit, a first controller configured to switch between a first power mode and a second power mode, and a power supply device. The power supply device includes a rectification unit, a smoothing capacitor, a transformer, a capacitor, a switching element, and a second controller. The second controller stops output of a pulse signal in a case where the voltage output from the power supply device is greater than a second voltage and a determined frequency is greater than a predetermined frequency, in the second power mode. The second controller starts the output of the pulse signal in a case where the voltage decreases and reaches the second voltage, in the second power mode.

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. At least one dielectric material portion is formed over the substrate adjacent to the alternating stack. Memory stack structures are formed through the alternating stack. A trench extending through the alternating stack and a via cavity extending through the at least one dielectric material portion are formed using a same anisotropic etch process. The via cavity is deeper than the trench and the via cavity extends into an upper portion of the substrate. The sacrificial material layers are replaced with electrically conductive layers using the trench as a conduit for an etchant and a reactant. A trench fill structure is formed in the trench, and a via structure assembly is formed in the via cavity using simultaneous deposition of material portions. A bonding pad may be formed on the bottom surface of the via structure assembly.

Abstract: A protection circuit protects a rectifier circuit from an inrush current inputted to a smoothing circuit. A short-circuiting circuit does not short the protection circuit while an inrush current may occur, and shorts it while an inrush current does not occur. A transformer has a primary winding, a secondary winding and an auxiliary winding. A delay circuit delays a timing at which an operation of a load connected to the auxiliary winding is started with respect to a timing at which an operation of the short-circuiting circuit is started. A rectifying and smoothing circuit generates an output voltage by rectifying and smoothing the secondary side voltage. The short-circuiting circuit is driven by the output voltage.

Abstract: A power source apparatus includes a plurality of first power sources, each connected to a load through a power supply line, and at least one second power source, which is a sub power source to be used when the first power source is unable to output a predetermined voltage. The second power source is connected in parallel to the power supply line of at least one of the first power source through a diode. The second power source is provided on an anode side of the diode, the load is configured to operate at a voltage equal to or more than a first voltage, the first power source outputs a second voltage higher than the first voltage, the second power source outputs a third voltage, which is higher than the first voltage, the voltage output through the diode from the second power source being lower than the second voltage.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. A memory film including a silicon nitride layer and a tunneling dielectric layer is formed in the memory opening, and an opening is formed through the memory film. A chemical oxide layer is formed on a physically exposed surface of an underlying semiconductor material portion. A silicon nitride ring can be formed by selectively growing a silicon nitride material from an annular silicon nitride layer portion of the silicon nitride layer while suppressing deposition of the silicon nitride material on the tunneling dielectric layer and on the chemical oxide layer. A vertical semiconductor channel can be formed by depositing a continuous semiconductor material layer on the underlying semiconductor material portion and the tunneling dielectric layer and on the silicon nitride ring.

Abstract: Provided is a power supply apparatus, which is capable of saving power at the time of low output power even in a configuration using an inrush current prevention resistor and a switch as an inrush current prevention circuit in order to increase power of a low power supply. An AC/DC power supply includes a rectifier configured to rectify an input AC voltage, a smoothing capacitor configured to smooth the rectified voltage, a resistor configured to limit an inrush current input to the smoothing capacitor, a relay configured to control whether to input a current to the resistor, and a current detection circuit. The AC/DC power supply further includes a converter connected at the subsequent stage of the smoothing capacitor and configured to adjust the voltage smoothed by the smoothing capacitor to a predetermined voltage.

Abstract: A three-dimensional memory device includes a source-level material layer stack located over a substrate that includes, from bottom to top, a lower source-level semiconductor layer, a semiconductor oxide tunneling layer, a source contact layer including a doped semiconductor material, and an upper source-level semiconductor layer, an alternating stack of electrically conductive layers and insulating layers located over the source-level material layer stack, and memory stack structures that extend through the alternating stack and into an upper portion of the lower source-level semiconductor layer, in which each memory stack structure includes a vertical semiconductor channel and a memory film laterally surrounding the vertical semiconductor channel, and each of the vertical semiconductor channels vertically extends through, and is electrically connected to, the source contact layer.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. A memory film including a silicon nitride layer and a tunneling dielectric layer is formed in the memory opening, and an opening is formed through the memory film. A chemical oxide layer is formed on a physically exposed surface of an underlying semiconductor material portion. A silicon nitride ring can be formed by selectively growing a silicon nitride material from an annular silicon nitride layer portion of the silicon nitride layer while suppressing deposition of the silicon nitride material on the tunneling dielectric layer and on the chemical oxide layer. A vertical semiconductor channel can be formed by depositing a continuous semiconductor material layer on the underlying semiconductor material portion and the tunneling dielectric layer and on the silicon nitride ring.

Abstract: In-process source-level material layers including a source-level sacrificial layer are formed over a substrate, and an alternating stack of insulating layers and spacer material layers and memory stack structures are formed over the in-process source-level layers. A backside trench is formed through the alternating stack, and a source cavity is formed by removing the source-level sacrificial layer employing an etchant provided through the backside trench. A source contact layer including a doped semiconductor material is formed on vertical semiconductor channels of the memory stack structures within the source cavity. The source contact layer includes an unfilled cavity, which is subsequently filled with a silicon nitride liner, a silicon oxide fill material and a semiconductor cap. A semiconductor oxide structure can be formed by filling voids in the silicon oxide fill material by oxidizing the semiconductor cap into a thermal semiconductor oxide material portion.