Patents by Inventor Takumi Moriyama

Takumi Moriyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11127655
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. At least one dielectric material portion is formed over the substrate adjacent to the alternating stack. Memory stack structures are formed through the alternating stack. A trench extending through the alternating stack and a via cavity extending through the at least one dielectric material portion are formed using a same anisotropic etch process. The via cavity is deeper than the trench and the via cavity extends into an upper portion of the substrate. The sacrificial material layers are replaced with electrically conductive layers using the trench as a conduit for an etchant and a reactant. A trench fill structure is formed in the trench, and a via structure assembly is formed in the via cavity using simultaneous deposition of material portions. A bonding pad may be formed on the bottom surface of the via structure assembly.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: September 21, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Takumi Moriyama, Hiroshi Sasaki, Yohei Masamori, Satoshi Shimizu
  • Publication number: 20210211056
    Abstract: A protection circuit protects a rectifier circuit from an inrush current inputted to a smoothing circuit. A short-circuiting circuit does not short the protection circuit while an inrush current may occur, and shorts it while an inrush current does not occur. A transformer has a primary winding, a secondary winding and an auxiliary winding. A delay circuit delays a timing at which an operation of a load connected to the auxiliary winding is started with respect to a timing at which an operation of the short-circuiting circuit is started. A rectifying and smoothing circuit generates an output voltage by rectifying and smoothing the secondary side voltage. The short-circuiting circuit is driven by the output voltage.
    Type: Application
    Filed: December 22, 2020
    Publication date: July 8, 2021
    Inventor: Takumi Moriyama
  • Publication number: 20210194251
    Abstract: A power source apparatus includes a plurality of first power sources, each connected to a load through a power supply line, and at least one second power source, which is a sub power source to be used when the first power source is unable to output a predetermined voltage. The second power source is connected in parallel to the power supply line of at least one of the first power source through a diode. The second power source is provided on an anode side of the diode, the load is configured to operate at a voltage equal to or more than a first voltage, the first power source outputs a second voltage higher than the first voltage, the second power source outputs a third voltage, which is higher than the first voltage, the voltage output through the diode from the second power source being lower than the second voltage.
    Type: Application
    Filed: December 16, 2020
    Publication date: June 24, 2021
    Inventor: Takumi Moriyama
  • Patent number: 11024645
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. A memory film including a silicon nitride layer and a tunneling dielectric layer is formed in the memory opening, and an opening is formed through the memory film. A chemical oxide layer is formed on a physically exposed surface of an underlying semiconductor material portion. A silicon nitride ring can be formed by selectively growing a silicon nitride material from an annular silicon nitride layer portion of the silicon nitride layer while suppressing deposition of the silicon nitride material on the tunneling dielectric layer and on the chemical oxide layer. A vertical semiconductor channel can be formed by depositing a continuous semiconductor material layer on the underlying semiconductor material portion and the tunneling dielectric layer and on the silicon nitride ring.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: June 1, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Takumi Moriyama, Yasushi Dowaki, Yuki Kasai, Satoshi Shimizu, Jayavel Pachamuthu
  • Patent number: 10971999
    Abstract: Provided is a power supply apparatus, which is capable of saving power at the time of low output power even in a configuration using an inrush current prevention resistor and a switch as an inrush current prevention circuit in order to increase power of a low power supply. An AC/DC power supply includes a rectifier configured to rectify an input AC voltage, a smoothing capacitor configured to smooth the rectified voltage, a resistor configured to limit an inrush current input to the smoothing capacitor, a relay configured to control whether to input a current to the resistor, and a current detection circuit. The AC/DC power supply further includes a converter connected at the subsequent stage of the smoothing capacitor and configured to adjust the voltage smoothed by the smoothing capacitor to a predetermined voltage.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: April 6, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takumi Moriyama
  • Patent number: 10916556
    Abstract: A three-dimensional memory device includes a source-level material layer stack located over a substrate that includes, from bottom to top, a lower source-level semiconductor layer, a semiconductor oxide tunneling layer, a source contact layer including a doped semiconductor material, and an upper source-level semiconductor layer, an alternating stack of electrically conductive layers and insulating layers located over the source-level material layer stack, and memory stack structures that extend through the alternating stack and into an upper portion of the lower source-level semiconductor layer, in which each memory stack structure includes a vertical semiconductor channel and a memory film laterally surrounding the vertical semiconductor channel, and each of the vertical semiconductor channels vertically extends through, and is electrically connected to, the source contact layer.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: February 9, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kiyohiko Sakakibara, Takumi Moriyama, Yu-Hsien Hsu
  • Publication number: 20210036004
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. A memory film including a silicon nitride layer and a tunneling dielectric layer is formed in the memory opening, and an opening is formed through the memory film. A chemical oxide layer is formed on a physically exposed surface of an underlying semiconductor material portion. A silicon nitride ring can be formed by selectively growing a silicon nitride material from an annular silicon nitride layer portion of the silicon nitride layer while suppressing deposition of the silicon nitride material on the tunneling dielectric layer and on the chemical oxide layer. A vertical semiconductor channel can be formed by depositing a continuous semiconductor material layer on the underlying semiconductor material portion and the tunneling dielectric layer and on the silicon nitride ring.
    Type: Application
    Filed: September 26, 2019
    Publication date: February 4, 2021
    Inventors: Takumi MORIYAMA, Yasushi DOWAKI, Yuki KASAI, Satoshi SHIMIZU, Jayavel PACHAMUTHU
  • Patent number: 10854627
    Abstract: In-process source-level material layers including a source-level sacrificial layer are formed over a substrate, and an alternating stack of insulating layers and spacer material layers and memory stack structures are formed over the in-process source-level layers. A backside trench is formed through the alternating stack, and a source cavity is formed by removing the source-level sacrificial layer employing an etchant provided through the backside trench. A source contact layer including a doped semiconductor material is formed on vertical semiconductor channels of the memory stack structures within the source cavity. The source contact layer includes an unfilled cavity, which is subsequently filled with a silicon nitride liner, a silicon oxide fill material and a semiconductor cap. A semiconductor oxide structure can be formed by filling voids in the silicon oxide fill material by oxidizing the semiconductor cap into a thermal semiconductor oxide material portion.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 1, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Takumi Moriyama, Satoshi Shimizu, Kiyohiko Sakakibara
  • Publication number: 20200286815
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. At least one dielectric material portion is formed over the substrate adjacent to the alternating stack. Memory stack structures are formed through the alternating stack. A trench extending through the alternating stack and a via cavity extending through the at least one dielectric material portion are formed using a same anisotropic etch process. The via cavity is deeper than the trench and the via cavity extends into an upper portion of the substrate. The sacrificial material layers are replaced with electrically conductive layers using the trench as a conduit for an etchant and a reactant. A trench fill structure is formed in the trench, and a via structure assembly is formed in the via cavity using simultaneous deposition of material portions. A bonding pad may be formed on the bottom surface of the via structure assembly.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 10, 2020
    Inventors: Takumi Moriyama, Hiroshi Sasaki, Yohei Masamori, Satoshi Shimizu
  • Patent number: 10720445
    Abstract: A lower source-level semiconductor layer, a sacrificial semiconductor layer, an upper source-level semiconductor layer, and an alternating stack of insulating layers and sacrificial material layers are sequentially formed over a substrate. An array of memory stack structures containing vertical semiconductor channels that extend through the alternating stack and into an upper portion of the lower source-level semiconductor layer is formed. A backside trench is formed through the alternating stack, and a source cavity is formed by removing the sacrificial semiconductor layer. A doped source contact layer is formed on each of the vertical semiconductor channels in the source cavity. A silicon nitride liner is formed on the doped source contact layer. The sacrificial material layers are replaced with electrically conductive layers. A dielectric wall structure is formed in the backside trench.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 21, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Satoshi Shimizu, Takumi Moriyama, Kiyohiko Sakakibara
  • Publication number: 20180358889
    Abstract: Provided is a power supply apparatus, which is capable of saving power at the time of low output power even in a configuration using an inrush current prevention resistor and a switch as an inrush current prevention circuit in order to increase power of a low power supply. An AC/DC power supply includes a rectifier configured to rectify an input AC voltage, a smoothing capacitor configured to smooth the rectified voltage, a resistor configured to limit an inrush current input to the smoothing capacitor, a relay configured to control whether to input a current to the resistor, and a current detection circuit. The AC/DC power supply further includes a converter connected at the subsequent stage of the smoothing capacitor and configured to adjust the voltage smoothed by the smoothing capacitor to a predetermined voltage.
    Type: Application
    Filed: June 7, 2018
    Publication date: December 13, 2018
    Inventor: Takumi Moriyama