Abstract: A multimedia decoder is provided that inserts synchronization words into elementary linear pulse-code modulation (LPCM) audio bitstreams. In one embodiment, the multimedia decoder includes a pre-parser, a memory, and an audio decoder module. The pre-parser receives a multimedia bitstream and separates it into an audio substream and a video substream, and inserts a synchronization words before each data packet in the audio substream while forming it into an elementary bitstream. The memory is coupled to the pre-parser to buffer the elementary audio bitstream, and the audio decoder module is coupled to the memory to retrieve the elementary audio bitstream and convert it into a digital audio signal. The inserted synchronization word may comprise between from four to ten bytes in length. In one particular implementation, the inserted synchronization word includes the ASCII representation of the letters LSILOGIC.

Abstract: The purpose of the present invention is to improve the rapid SPU playback scheme in a DVD player. In order to achieve this end, the method in accordance with the invention comprises the steps of: comparing the system time clock (STC) with the execution time of an instruction set that provides display control in the sub-picture units (SP_DCSQ_STM_N), forcing the display of pixel data (PXD) contained in a sub-picture unit to suspend operation and to proceed to instruction interpretation of the instruction set in a next sub-picture unit if said comparison means determines, when the sub-picture units are being rapidly played back, that the system time clock performing a rapid increment operation has a greater value than the execution time of the instruction set at least one ahead (SP_DCSQ_STM_N+1) and continuously repeating the instruction interpretation until the execution time of the instruction set coincides with the system time clock.

Abstract: An audio decoder which includes a coefficient memory and an arithmetic logic unit (ALU) can implement an efficient method for calculating a gain value specified by a range control field. In one embodiment, the audio decoder comprises coefficient memory, an ALU, frame control logic, and ALU control logic. The frame control logic extracts a range control field value from an audio packet header and provides it to the ALU control logic. The ALU control logic takes the binary representation of the range control field value and uses it to provide a sequence of addresses to the coefficient memory. In response to the sequence of addresses, the coefficient memory provides a sequence of pre-calculated factors to the ALU. The ALU control logic further directs the ALU to determine the product of the pre-calculated factors in the sequence. As a final step in finding the gain value, the ALU control logic may provide a shift instruction to the ALU.

Abstract: An audio decoder converts a linear PCM audio data packet into two concurrently provided digital audio sample sequences: a high-quality sequence and a decimated sequence. In one embodiment, the audio decoder is part of an audio system that further includes two audio devices. The first audio device is configured to produce an audio signal from a 96 kHz sequence, and the second audio device expects a 48 kHz sequence. The audio decoder includes an input interface, an arithmetic logic unit (ALU), and two output buffers. The input interface is configured to receive a linear PCM audio data packet and to reconfigure bytes as necessary to reconstruct a sequence of unscaled audio samples. The ALU multiplies each of the unscaled audio samples by a gain factor and buffers the resulting scaled audio sample sequence in a first output buffer.

Abstract: An audio decoder is described that can concurrently produce two synchronized outputs of a digital audio stream at different sampling rates and can provide for seamless switching between the rates. In one embodiment, the audio decoder includes a first output buffer, an arithmetic logic unit (ALU), a second output buffer, and a control module. The first audio buffer is configured to buffer a sequence of digital audio samples and to provide the first sequence of digital audio samples to an output device at 96 kHz. The arithmetic logic unit (ALU) is coupled to the first output buffer to retrieve the first sequence of digital audio samples and to convert the first sequence of digital audio samples into a decimated sequence of digital audio samples. The second output buffer is coupled to the ALU to buffer the decimated sequence of digital audio and to provide the decimated sequence of digital audio samples to a second output device at 48 kHz.