Abstract: A shift register circuit has a plurality of shift pulse generation circuits, and a scanning voltage generation circuit has a plurality of base circuits. The base circuits are presented with a first shift pulse generated by a shift pulse generation circuit, and a scanning line clock. The base circuits have a first transistor in which the first shift pulse is input to a first electrode, and a first power supply voltage is input to a control electrode; and a second transistor in which a control electrode is connected to a second electrode in the first transistor, a scanning line clock is input to the first electrode, and the second electrode is connected to a scanning voltage output terminal. The base circuits output a selected scanning voltage synchronized with the scanning line clock from the scanning voltage output terminal when the first shift pulse is at a first voltage level.

Abstract: A display device which enhances time-wise likelihood for a leak current from a floating memory node by increasing the number of writings of a voltage to a floating memory node. A vertical driver includes: a shift register including basic circuits which output common electrode driving pulses based on a transfer; and a common electrode driver including common basic circuits which receive the common electrode driving pulses and the transfer clock. Each common basic circuit includes: a circuit A which fetches an AC signal based on the common electrode driving pulse; a circuit B which outputs, based on the AC signal, a first common voltage or a second common voltage which differs from the first common voltage in voltage level to the common electrodes corresponding to the AC signal; and a circuit C which holds a state of the circuit B based on the transfer clock.

Abstract: In a display device which includes a driver circuit having a shift register circuit, the shift register circuit is constituted of basic circuits in plural stages. Each basic circuit is constituted of a circuit A, a circuit B and a circuit C. The circuit A fetches a first drive clock (or a second drive clock) inputted from the outside when transfer data is inputted to the circuit A from a circuit of preceding stage, outputs the transfer data as a shift output of own stage, and transfers the transfer data to the circuit B. The circuit B transfers the transfer data to the circuit A of the basic circuit of the succeeding stage, and resets the circuit C. The circuit C resets the circuit A and the circuit B in synchronism with the first drive clock (or the second drive clock) generated at next timing or succeeding timing of the first drive clock.

Abstract: A display device is provided in which at least first and second thin film transistors are formed on a substrate, including a gate electrode formed on a semiconductor layer with a gate insulating film in between. The semiconductor layer is divided into individual regions for each film transistor, and is provided with a common region and LDD regions between a channel region and a drain region, as well as between the channel region and a source region. The gate electrode is formed as an integrated gate electrode for the first and second thin film transistors that faces the common region, the channel region and the LDD regions of the first thin film transistor and the channel region and the LDD regions of the second thin film transistor.

Abstract: Provided are a display device and a method of driving the same, improving display quality by suppressing abnormal changes resulting from parasitic capacitance. The display device includes first and second pixel circuits having first and second switching elements and first and second display electrodes; and a display control voltage supply unit supplying a display control voltage to the first and second display electrodes. In a first write period, the display control voltage supply unit turns ON the first and second switching elements and supplies a display control voltage corresponding to display data of the first pixel circuit to the first and second display electrodes. In a second write period, the display control voltage supply unit maintains the switch of the second switching element to be in the ON state and supplies a display control voltage corresponding to display data of the second pixel circuit to the second display electrode.

Abstract: An object of the present invention is to provide a display device where small thin film transistors with a lower off current can be formed.

Abstract: A display device which enhances time-wise likelihood for a leak current from a floating memory node by increasing the number of writing of a voltage to a floating memory node is provided. In the display device, a vertical driver circuit includes a shift register circuit and a common electrode driver circuit. The shift register circuit is constituted of a plurality of basic circuits which outputs common electrode driving pulses based on a transfer clock inputted from the outside. The common electrode driver circuit is constituted of a plurality of common basic circuits to which the respective common electrode driving pulses outputted from the respective basic circuits of the shift register circuit and the transfer clock are inputted.

Abstract: In a display device which includes a driver circuit having a shift register circuit, the shift register circuit is constituted of basic circuits in plural stages. Each basic circuit is constituted of a circuit A, a circuit B and a circuit C. The circuit A fetches a first drive clock (or a second drive clock) inputted from the outside when transfer data is inputted to the circuit A from a circuit of preceding stage, outputs the transfer data as a shift output of own stage, and transfers the transfer data to the circuit B. The circuit B transfers the transfer data to the circuit A of the basic circuit of the succeeding stage, and resets the circuit C. The circuit C resets the circuit A and the circuit B in synchronism with the first drive clock (or the second drive clock) generated at next timing or succeeding timing of the first drive clock.

Abstract: A shift register circuit has a plurality of shift pulse generation circuits, and a scanning voltage generation circuit has a plurality of base circuits. The base circuits are presented with a first shift pulse generated by a shift pulse generation circuit, and a scanning line clock. The base circuits have a first transistor in which the first shift pulse is input to a first electrode, and a first power supply voltage is input to a control electrode; and a second transistor in which a control electrode is connected to a second electrode in the first transistor, a scanning line clock is input to the first electrode, and the second electrode is connected to a scanning voltage output terminal. The base circuits output a selected scanning voltage synchronized with the scanning line clock from the scanning voltage output terminal when the first shift pulse is at a first voltage level.