Abstract: In order to reduce the amount of consumption of a back-end bandwidth in a storage apparatus, a computer system includes: a first storage device; and a second storage device that is coupled to the first controller through a first interface and is coupled to the second controller through a second interface. The first controller receives data from a host computer through a first communication channel; write the received data into the first storage device; identify part of the received data as first data, the part satisfying a preset particular condition; and write a replica of the first data as second data into the second storage device. The second controller reads the second data from the second storage device in response to a Read request received from the host computer through a second communication channel; and transmit the second data to the host computer through the second communication channel.

Abstract: In order to reduce the amount of consumption of a back-end bandwidth in a storage apparatus, a computer system includes: a first storage device; and a second storage device that is coupled to the first controller through a first interface and is coupled to the second controller through a second interface. The first controller receives data from a host computer through a first communication channel; write the received data into the first storage device; identify part of the received data as first data, the part satisfying a preset particular condition; and write a replica of the first data as second data into the second storage device. The second controller reads the second data from the second storage device in response to a Read request received from the host computer through a second communication channel; and transmit the second data to the host computer through the second communication channel.

Abstract: In order to reduce the amount of consumption of a back-end bandwidth in a storage apparatus, a computer system includes: a first storage device; and a second storage device that is coupled to the first controller through a first interface and is coupled to the second controller through a second interface. The first controller receives data from a host computer through a first communication channel; write the received data into the first storage device; identify part of the received data as first data, the part satisfying a preset particular condition; and write a replica of the first data as second data into the second storage device. The second controller reads the second data from the second storage device in response to a Read request received from the host computer through a second communication channel; and transmit the second data to the host computer through the second communication channel.

Abstract: In order to reduce the amount of consumption of a back-end bandwidth in a storage apparatus, a computer system includes: a first storage device; and a second storage device that is coupled to the first controller through a first interface and is coupled to the second controller through a second interface. The first controller receives data from a host computer through a first communication channel; write the received data into the first storage device; identify part of the received data as first data, the part satisfying a preset particular condition; and write a replica of the first data as second data into the second storage device. The second controller reads the second data from the second storage device in response to a Read request received from the host computer through a second communication channel; and transmit the second data to the host computer through the second communication channel.

Abstract: A semiconductor device having an SRAM macro which has a power-off function and facilitates a design associated with a change in storage capacity is provided. The semiconductor device has plural layout units each including a memory array having plural memory cells in an SRAM, a first peripheral circuit that writes data into the memory array and reads the data from the memory array, and a switch group that disconnects the memory array and the first peripheral circuit, and power wires.

Abstract: A semiconductor device having an SRAM macro which has a power-off function and facilitates a design associated with a change in storage capacity is provided. The semiconductor device has plural layout units each including a memory array having plural memory cells in an SRAM, a first peripheral circuit that writes data into the memory array and reads the data from the memory array, and a switch group that disconnects the memory array and the first peripheral circuit, and power wires.