Abstract: In a storage system including an FPGA having a logic which executes a prescribed processing and a plurality of devices coupled to the FPGA via a bus, the logic of the FPGA is configured to: attempt to access the plurality of devices and, based on a status of access to the devices, determine whether or not there is an abnormality in the access to the devices; and when it is determined that there is an abnormality in the access to a device, reset an IF unit for performing a communication processing via a bus of the device.

Abstract: A device communication control module, which performs I/O conversion for accessing a PCIe device connected to a different PCIe domain from a PCIe domain to which a CPU belongs, includes a device management table that holds a CFG address and an MMIO address corresponding to each PCIe device, and a virtual device corresponding to each PCIe device. When the CPU issues CFG access to the virtual device, the device communication control module returns an MMIO address corresponding to each PCIe device to the CPU based on information about the CFG access.

Abstract: In a storage system including an FPGA having a logic which executes a prescribed processing and a plurality of devices coupled to the FPGA via a bus, the logic of the FPGA is configured to: attempt to access the plurality of devices and, based on a status of access to the devices, determine whether or not there is an abnormality in the access to the devices; and when it is determined that there is an abnormality in the access to a device, reset an IF unit for performing a communication processing via a bus of the device.