Patents by Inventor Takuo Funaya

Takuo Funaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11063009
    Abstract: There is a need to improve reliability of the semiconductor device. A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h2 of the solder layer is measured from the upper surface of the resist layer. Thickness h1 is greater than or equal to a half of thickness h2 and is smaller than or equal to thickness h2.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: July 13, 2021
    Assignee: Renesas Electronics Corporation
    Inventors: Kenji Sakata, Toshihiko Akiba, Takuo Funaya, Hideaki Tsuchiya, Yuichi Yoshida
  • Patent number: 10483199
    Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a wiring M3 formed on an interlayer insulator IL3, and a coil CL2 and a wiring M4 formed on the interlayer insulator IL4. Moreover, a distance DM4 between the coil CL2 and the wiring M4 is longer than a distance DM3 between the coil CL2 and the wiring M3 (DM4>DM3). Furthermore, the distance DM3 between the coil CL2 and the wiring M3 is set to be longer than a sum of a film thickness of the interlayer insulator IL3 and a film thickness of the interlayer insulator IL4, which are positioned between the coil CL1 and the coil CL2. In this manner, it is possible to improve an insulation withstand voltage between the coil CL2 and the wiring M4 or the like, where a high voltage difference tend to occur.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: November 19, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Takayuki Igarashi, Takuo Funaya
  • Patent number: 10157974
    Abstract: A semiconductor device includes a semiconductor substrate having a main surface, a first insulating film formed on the main surface, a first coil formed on the first insulating film, a second insulating film formed on the first coil and having a first main surface and first side surfaces continuous with the first main surface, a third insulating film formed on the first main surface of the second insulating film and having a second main surface and second side surfaces continuous with the second main surface, and a second coil formed on the second main surface of the third insulating film. The second insulating film and the third insulating film are formed as a laminated insulating film together. A thickness of the second coil is greater than a thickness of the first coil in a thickness direction of the semiconductor substrate.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: December 18, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takuo Funaya, Hiromi Shigihara, Hisao Shigihara
  • Publication number: 20180337124
    Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a wiring M3 formed on an interlayer insulator IL3, and a coil CL2 and a wiring M4 formed on the interlayer insulator IL4. Moreover, a distance DM4 between the coil CL2 and the wiring M4 is longer than a distance DM3 between the coil CL2 and the wiring M3 (DM4>DM3). Furthermore, the distance DM3 between the coil CL2 and the wiring M3 is set to be longer than a sum of a film thickness of the interlayer insulator IL3 and a film thickness of the interlayer insulator IL4, which are positioned between the coil CL1 and the coil CL2. In this manner, it is possible to improve an insulation withstand voltage between the coil CL2 and the wiring M4 or the like, where a high voltage difference tend to occur.
    Type: Application
    Filed: July 30, 2018
    Publication date: November 22, 2018
    Inventors: Takayuki IGARASHI, Takuo FUNAYA
  • Patent number: 10128125
    Abstract: A semiconductor device including: a semiconductor substrate; a first coil formed on the semiconductor substrate via a first insulation film; a second insulation film formed on the semiconductor substrate so as to cover the first insulation film and the first coil; a first pad formed on the second insulation film and disposed at a position not overlapped with the first coil in a planar view; a laminated insulation film formed on the second insulation film, the laminated insulation film having a first opening from which the first pad is exposed; a second coil formed on the laminated insulation film and disposed above the first coil; and a first wiring formed on the laminated insulation film including an upper portion of the first pad exposed from the first opening, the first wiring being electrically connected to the first pad.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: November 13, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takuo Funaya, Takayuki Igarashi
  • Publication number: 20180310529
    Abstract: A method for manufacturing an electronic apparatus functioning as a component of a wireless communication system includes providing a lower part formed with a first concave portion, a second concave portion spaced away from the first concave portion, and a third concave portion which couples the first concave portion and the second concave portion, providing an upper part for sealing the first concave portion, the second concave portion, and the third concave portion formed in the lower part, providing a module unit including a sensor which detects a physical quantity, and a radio communication unit which transmits data based on an output signal from the sensor, providing a battery for supplying power to the module unit, coupling the module unit and the battery by a wiring, and after the coupling the module unit and the battery, arranging the module unit in the first concave portion of the lower part.
    Type: Application
    Filed: July 9, 2018
    Publication date: November 1, 2018
    Inventors: Takuo Funaya, Tomohiro NISHIYAMA, Hiroki SHIBUYA, Manabu OKAMOTO
  • Publication number: 20180294239
    Abstract: There is a need to improve reliability of the semiconductor device. A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h2 of the solder layer is measured from the upper surface of the resist layer. Thickness h1 is greater than or equal to a half of thickness h2 and is smaller than or equal to thickness h2.
    Type: Application
    Filed: February 5, 2018
    Publication date: October 11, 2018
    Inventors: Kenji SAKATA, Toshihiko AKIBA, Takuo FUNAYA, Hideaki TSUCHIYA, Yuichi YOSHIDA
  • Patent number: 10085425
    Abstract: An electronic apparatus is provided which, even when the electronic apparatus configuring a node is implanted in the body of an object animal, makes the object animal hard to feel stress and can acquire effective data about the natural behavior and state of the object animal. As shown in FIG. 12, a module unit and a battery are arranged separated from each other. That is, an electronic apparatus according to the present embodiment 1 adopts a case including a first capacity part and a second capacity part both arranged separated from each other to thereby accommodate the module unit in an internal space of the first capacity part and accommodate the battery in an internal space of the second capacity part.
    Type: Grant
    Filed: June 27, 2015
    Date of Patent: October 2, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takuo Funaya, Tomohiro Nishiyama, Hiroki Shibuya, Manabu Okamoto
  • Patent number: 10062642
    Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a wiring M3 formed on an interlayer insulator IL3, and a coil CL2 and a wiring M4 formed on the interlayer insulator IL4. Moreover, a distance DM4 between the coil CL2 and the wiring M4 is longer than a distance DM3 between the coil CL2 and the wiring M3 (DM4>DM3). Furthermore, the distance DM3 between the coil CL2 and the wiring M3 is set to be longer than a sum of a film thickness of the interlayer insulator IL3 and a film thickness of the interlayer insulator IL4, which are positioned between the coil CL1 and the coil CL2. In this manner, it is possible to improve an insulation withstand voltage between the coil CL2 and the wiring M4 or the like, where a high voltage difference tend to occur.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: August 28, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Takayuki Igarashi, Takuo Funaya
  • Publication number: 20180069073
    Abstract: A semiconductor device includes a semiconductor substrate having a main surface, a first insulating film formed on the main surface, a first coil formed on the first insulating film, a second insulating film formed on the first coil and having a first main surface and first side surfaces continuous with the first main surface, a third insulating film formed on the first main surface of the second insulating film and having a second main surface and second side surfaces continuous with the second main surface, and a second coil formed on the second main surface of the third insulating film. The second insulating film and the third insulating film are formed as a laminated insulating film together. A thickness of the second coil is greater than a thickness of the first coil in a thickness direction of the semiconductor substrate.
    Type: Application
    Filed: October 31, 2017
    Publication date: March 8, 2018
    Inventors: Takuo Funaya, Hiromi Shigihara, Hisao SHIGIHARA
  • Publication number: 20180061662
    Abstract: A semiconductor device including: a semiconductor substrate; a first coil formed on the semiconductor substrate via a first insulation film; a second insulation film formed on the semiconductor substrate so as to cover the first insulation film and the first coil; a first pad formed on the second insulation film and disposed at a position not overlapped with the first coil in a planar view; a laminated insulation film formed on the second insulation film, the laminated insulation film having a first opening from which the first pad is exposed; a second coil formed on the laminated insulation film and disposed above the first coil; and a first wiring formed on the laminated insulation film including an upper portion of the first pad exposed from the first opening, the first wiring being electrically connected to the first pad.
    Type: Application
    Filed: October 20, 2017
    Publication date: March 1, 2018
    Inventors: Takuo FUNAYA, Takayuki Igarashi
  • Patent number: 9818815
    Abstract: A semiconductor device includes a semiconductor substrate having a main surface; a first coil formed on the main surface; a first insulating film formed over the first coil and having a first main surface; a second insulating film formed on the first main surface of the first insulating film and having a second main surface; and a second coil formed on the second main surface of the second insulating film, wherein the first main surface of the first insulating film has a first area on which the second insulating film is formed, and has a second area without the first area in a plan view, and wherein the second insulating film is surrounded with the second area in the plane view.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: November 14, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takuo Funaya, Hiromi Shigihara, Hisao Shigihara
  • Publication number: 20170317024
    Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a wiring M3 formed on an interlayer insulator IL3, and a coil CL2 and a wiring M4 formed on the interlayer insulator IL4. Moreover, a distance DM4 between the coil CL2 and the wiring M4 is longer than a distance DM3 between the coil CL2 and the wiring M3 (DM4>DM3). Furthermore, the distance DM3 between the coil CL2 and the wiring M3 is set to be longer than a sum of a film thickness of the interlayer insulator IL3 and a film thickness of the interlayer insulator IL4, which are positioned between the coil CL1 and the coil CL2. In this manner, it is possible to improve an insulation withstand voltage between the coil CL2 and the wiring M4 or the like, where a high voltage difference tend to occur.
    Type: Application
    Filed: June 7, 2017
    Publication date: November 2, 2017
    Inventors: Takayuki IGARASHI, Takuo FUNAYA
  • Patent number: 9805950
    Abstract: A method of manufacturing a semiconductor device including: (a) forming a first insulation film on a semiconductor substrate; (b) forming a first coil on the first insulation film; (c) forming a second insulation film on the first insulation film so as to cover the first coil; (d) forming a first pad on the second insulation film at a position not overlapped with the first coil in a planar view; (e) forming a laminated insulation film on the second insulation film, the laminated insulation film having a first opening from which the first pad is exposed; and (f) forming a second coil and a first wiring on the laminated insulation film, wherein the second coil is disposed above the first coil, the first coil and the second coil are not connected by a conductor but magnetically coupled to each other, the first wiring is formed from an upper portion of the first pad to an upper portion of the laminated insulation film and is electrically connected to the first pad, and the laminated insulation film includes a sil
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: October 31, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Takuo Funaya, Takayuki Igarashi
  • Patent number: 9711451
    Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a wiring M3 formed on an interlayer insulator IL3, and a coil CL2 and a wiring M4 formed on the interlayer insulator IL4. Moreover, a distance DM4 between the coil CL2 and the wiring M4 is longer than a distance DM3 between the coil CL2 and the wiring M3 (DM4>DM3). Furthermore, the distance DM3 between the coil CL2 and the wiring M3 is set to be longer than a sum of a film thickness of the interlayer insulator IL3 and a film thickness of the interlayer insulator IL4, which are positioned between the coil CL1 and the coil CL2. In this manner, it is possible to improve an insulation withstand voltage between the coil CL2 and the wiring M4 or the like, where a high voltage difference tend to occur.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: July 18, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Takayuki Igarashi, Takuo Funaya
  • Publication number: 20170194164
    Abstract: A method of manufacturing a semiconductor device including: (a) forming a first insulation film on a semiconductor substrate; (b) forming a first coil on the first insulation film; (c) forming a second insulation film on the first insulation film so as to cover the first coil; (d) forming a first pad on the second insulation film at a position not overlapped with the first coil in a planar view; (e) forming a laminated insulation film on the second insulation film, the laminated insulation film having a first opening from which the first pad is exposed; and (f) forming a second coil and a first wiring on the laminated insulation film, wherein the second coil is disposed above the first coil, the first coil and the second coil are not connected by a conductor but magnetically coupled to each other, the first wiring is formed from an upper portion of the first pad to an upper portion of the laminated insulation film and is electrically connected to the first pad, and the laminated insulation film includes a sil
    Type: Application
    Filed: March 17, 2017
    Publication date: July 6, 2017
    Inventors: Takuo FUNAYA, Takayuki IGARASHI
  • Patent number: 9653396
    Abstract: A coil CL1 is formed on a semiconductor substrate SB via a first insulation film, a second insulation film is formed so as to cover the first insulation film and the coil CL1, and a pad PD1 is formed on the second insulation film. A laminated film LF having an opening OP1 from which the pad PD1 is partially exposed is formed on the second insulation film, and a coil CL2 is formed on the laminated insulation film. The coil CL2 is disposed above the coil CL1, and the coil CL2 and the coil CL1 are magnetically coupled to each other. The laminated film LF is composed of a silicon oxide film LF1, a silicon nitride film LF2 thereon, and a resin film LF3 thereon.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: May 16, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Takuo Funaya, Takayuki Igarashi
  • Patent number: 9536828
    Abstract: On a semiconductor substrate, coils CL5 and CL6 and pads PD5, PD6, and PD7 are formed. The coil CL5 and the coil CL6 are electrically connected in series between the pad PD5 and the pad PD6, and the pad PD7 is electrically connected between the coil CL5 and the coil CL6. The coil magnetically coupled to the coil CL5 is formed just below the coil CL5, the coil magnetically coupled to the coil CL6 is formed just below the coil CL6, and they are connected in series. When a current is flowed in the coils connected in series formed just below the coils CL5 and CL6, directions of induction current flowing in the coils CL5 and CL6 are opposed to each other in the coils CL5 and CL6.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: January 3, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichi Uchida, Hirokazu Nagase, Takuo Funaya
  • Patent number: 9502489
    Abstract: Provided is a semiconductor device having improved reliability. Over a semiconductor substrate, a first coil is formed via a first insulating film. A second insulating film is formed so as to cover the first insulating film and the first coil. Over the second insulating film, a pad is formed. Over the second insulating film, a multi-layer film having an opening exposing a part of the pad is formed. Over the multi-layer insulating film, a second coil is formed. The second coil is placed over the first coil. The second and first coils are magnetically coupled to each other. The multi-layer film includes a silicon dioxide film, a silicon nitride film over the silicon dioxide film, and a resin film over the silicon nitride film.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: November 22, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takuo Funaya, Takayuki Igarashi
  • Publication number: 20160087025
    Abstract: A semiconductor device includes a semiconductor substrate having a main surface; a first coil formed on the main surface; a first insulating film formed over the first coil and having a first main surface; a second insulating film formed on the first main surface of the first insulating film and having a second main surface; and a second coil formed on the second main surface of the second insulating film, wherein the first main surface of the first insulating film has a first area on which the second insulating film is formed, and has a second area without the first area in a plan view, and wherein the second insulating film is surrounded with the second area in the plane view.
    Type: Application
    Filed: December 7, 2015
    Publication date: March 24, 2016
    Inventors: Takuo Funaya, Hiromi Shigihara, Hisao SHIGIHARA